This paper gives the method to reduce switching power in the CMOS circuit using multistage clock network. Power consumption is the major problem that we face in the portable devices. In this reduction technique, we investigate the problem of high power consumption of CMOS circuits and introduced a method to reduce power, using multistage clock networks. The clock with variable phase is provided to the logic circuits. The clock phase variation is selected by lookup table controller, to reduce the unnecessary switching. The simulation of proposed technique is analyzed using tanner EDA tool. This analysis is carried out with multistage clock network and without multistage clock network. The lookup table based multistage clock controller provides better reduction in power and delay compared to previous stages.
ABSTRACT: The increase in demand for low power devices led to research of solutions for the reduction of energy and power consumption. The switching events during charging-discharging of load capacitor cause increase in power consumption/dissipation. Adiabatic logic is an alternative approach for reducing the power consumption/dissipation. It offers a way to utilise the stored energy from the load capacitor by recycling to the power supply. Inspite of the complexity of circuits, the logic provides good power saving. The simulation results of adiabatic logic circuits are compared to logic of CMOS circuits indicating the former is more advantageous.
In deep submicron technologies, leakage power becomes a key for a low power design due to its ever increasing proportion in chip’s total power consumption. Power dissipation is an important consideration in the design of CMOS VLSI circuits. High power consumption leads to reduction in battery life in case of battery powered applications and affects reliability packaging and cooling costs. We propose a technique called LCPMOS for designing CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. LCPMOS, a technique to tackle the leakage problem in CMOS circuits, uses single additional leakage control transistor, driven by the output from the pull up and pull down networks, which is placed in a path from pull down network to ground which provides the additional resistance thereby reducing the leakage current in the path from supply to ground. The main advantage as compared to other techniques is that LCPMOS technique does not require any additional control and monitoring circuitry, thereby limits the area and also decreases the power dissipation in active state. Along with this, the other advantage with LCPMOS technique is that it reduces the leakage power to an extent of 91.54%, which is more efficient in aspects of area and power dissipation compared to other leakage power reduction techniques.
The multi-threshold voltage CMOS (MTCMOS)  technique is also a kind of power gating technique which uses high threshold transistors as a sleep transistors and low threshold voltage transistors are used to implement the logic. In dual threshold voltage CMOS technique , transistor of different threshold voltages are used. Low threshold voltage transistors are used for the gates on the critical path to maintain the performance, while high threshold voltage transistors are used for the gates on the non-critical path for reduction of the leakage current. Stacking effect has been defined in , when more than one transistor in the stack is turned off, stacking of series connected transistors used for the reduction of the sub threshold leakage currents. This effect is called the. Forced stacking  yields the stacking effect by inserting extra transistor for every input of the gate in both PMOS and NMOS networks. So in the forced stacking two transistor are always off for every off input of the gate, which reduced the leakage current.
Abstract— In the design of digital integrated circuits, power consumption is an important criterion. That indicates that low power circuits are now a days, emerging as an utmost priority in modern VLSI design. This is in contrast with the early 70s, when providing high speed operation with the least area was the main aim of design. But of course, other factors like area, propagation delay, leakage current etc. also can not be ignored in the design process. Out of these techniques, some are quite efficient in reducing static (leakage) power .This paper is prepared to review the available low power design techniques that are pivotal in designing various digital circuits.
For testing purposes it is proposed that the bandgap reference power supply be supplied externally. With an independent power supply the bandgap reference will settle independently without the need for POR or power up supervision. For a prototype IC, it is proposed that all terminals of the bandgap be isolated from the regulator structure. Isolation of blocks in the prototype means that each input and output of the bandgap and rectifier circuits will be con- nected to pins on the prototype IC. An entirely batteryless configuration can be tested with the prototype by externally connecting the power supply of the bandgap reference to the regula- tor output. In simulation, the bondpads and bonding wire of the IC are modelled as parasitic resistance and capacitance components. At high frequencies the parasitics of packaging and interconnects degrade circuit performance. Since the output of the circuit operates at DC the parasitic capacitance of bondpad and bonding wire have a negligible e ff ect on circuit perfor- mance. AC input voltage is at a frequency of approximately 1 GHz. For adequate power transfer from signal source to input of the rectifier, a matching network will need to be developed based on measurements of the fabricated rectifier prototype.
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 Y. Taur, “CMOS design near the limit of scaling,” IBM J.Res. & Dev., Vol. 46 No. 2/3, pp. 213-222, Mar/May 2002.  S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu,J. Yamada, “1-V Power Supply High-speed Digital Circuit Technology with Multi-threshold-Voltage CMOS,” JSSC, vol. 30, no. 8, pp. 847-854, August 1995.
Technology scaling of transistor feature size has provided a remarkable advancement in silicon industry for the last three decades. The demand and popularity of portable electronics is driving designers to strive for small silicon area, higher speeds, low power dissipation and reliability. Compared to static CMOS logic, dynamic logic offers good performance. Wide fan-in logic such as domino circuits is used in high-performance applications. Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favoured in high performance designs because of the speed advantage offered over static CMOS logic circuits. This paper compares static CMOS, domino (dynamic) logic design implementations of 16-bit Ripple carry adder, 16-bit Comparator and Linear Feedback Shift Register (LFSR) in terms of CMOS layout power consumption, delay, power delay product, area for 65 nm and 45 nm technologies. The techniques are compared by performing detailed transistor simulations on benchmark circuits using Microwind 3 and DSCH3 CMOS layout CAD tools.
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Historically, VLSI designers have used speed as the performance metric. High gains, in terms of performance and silicon area, have been made for digital processors, microprocessors, DSPs (Digital Signal Processors), ASICs (Application Specific ICs), etc. In general, small area and high performance are two conflicting constraints . The power consumed for any given function in CMOS circuit must be reduced for either of the two different reasons: One of these reasons is to reduce heat dissipation in order to allow a large density of functions to be incorporated on an IC chip. Any amount of power dissipation is worthwhile as long as it doesn’t degrade overall circuit performance. The other reason is to save energy in battery operated instruments same as electronic watches where average power is in microwatts In CMOS circuits, the power consumption is proportional to switching activity, capacitive loading and the square of the supply voltage .
In this work principles are presented which allow to inte- grate adiabatic function blocks into static CMOS circuits. A synchronized converter is used to generate the dual rail encoded trapezoidal signals which are necessary for the con- sidered adiabatic families PFAL, ECRL and 2N-2N2P. Inside the converter a comparator is used to extract the clock signal for synchronizing the input signal. This clock signal can be used for every timing issue between the two circuitries. The robustness of this signal is an issue of oscillator and com- parator design. The oscillator must provide the circuit with four phases which have an exact difference of 90 degrees, otherwise the energy dissipation increases. The compara- tor’s delay is well known and can be adjusted regarding to the timing conditions. By combining the serial input data to 4bit words, the input rate can be increased by a factor of four. This principle can be used to minimize pads at the input. It is also worth noticing that the throughput rate of adiabatic cir- cuits is up to four times higher than the adiabatic frequency because of the 4-phase system.
Leakage current is a primary concern for low-power, high- performance digital CMOS circuits. The exponential increase in the leakage component of the total chip power can be attributed to threshold voltage scaling, which is essential to maintain high performance in active mode, since supply voltages are scaled. Numerous design techniques have been proposed to reduce standby leakage in digital circuits. Leakage power has become a serious concern in nanometer CMOS technologies, and power-gating has shown to offer a viable solution to the problem with a small penalty in performance .
This paper describes a high speed boosted CMOS differential logic which is used in ripple carry adders. The proposed logic style improves switching speed by boosting the gate–source voltage of transistors along timing-critical signal paths. Test sets of logic gates were designed in a 0.18-μm CMOS process, whose comparison results indicated that the energy–delay product of the proposed logic style was improved by up to 50% compared with conventional logic styles at supply voltage of 1.8V. The experimental result for 32 bit ripple carry adder using the proposed logic style revealed that the addition time is reduced as compared with the conventional CMOS circuits.
type of the integrated circuit. There is a trade of between the power and performance of the integrated circuit. The main aim of this paper is to maintain performance of the integrated circuit while reducing the power consumption because the cost of the system is dependent on the power. Power dissipation in CMOS circuits is the combination of three main components.
Inherent low power utilization of Complementary Metal Oxide Semiconductor (CMOS) innovation is one of the key highlights that prompted the immense achievement of this innovation. Due to this the circuit designers could concentrate on maximizing the circuit performance along with the reduction in the circuit area. CMOS technology has very good scaling properties due to this there is a decrease in the size of the IC’s which take into account increasingly
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ABSTRACT : Comparator is one of the most essential analog circuits required in many analog integrated circuits. It is used for the comparison between two similar or different electrical signals with reference. The design of Comparator becomes an essential issue when technology is scaled down. Due to the non-linear behavior of threshold voltage (VT) when the scale of technology is reduced, performance of Comparator is affected. Many versions of comparator are proposed to acquire enticing output in sub-micron and deep sub-micron technologies. The selection of particular topology is dependent upon the requirements and application. In this we will simulate all types mentioned types of comparators and analyze them on the basis of different characteristics of comparator like : power dissipation , offset voltage , delay, speed and no. of transistor used. The simulated in HSPICE.
The CMOS inverter is truly very important for all the digital designs. The electrical behaviour of complex circuits can be almost completely derived by deriving the results from inverters. Figure 2 shows the circuit diagram of a static CMOS inverter . When Vin is high and equal to VDD, the NMOS transistor is on, while the PMOS is off. A direct path exists between Vout and the ground node, resulting in a steady-state value of 0 V. On the other hand, when the input voltage is low (0 V), NMOS and PMOS transistors are off and on, respectively. A path exists between Vdd and Vout , yielding a high output voltage.
activity of the circuits. It is observed that the dynamic realization has more activity than static realizations , . The input signal slopes and transistor sizing are strongly effects the short circuit current. The reduction in short circuit current is possible by giving steep and balanced input signal slopes. A good logic style allows decoupling of input and outputs of the logic gates, good driving capability and full signal swings so that it is easy to use and work reliably. Thereby for cell based designs functionality and synthesis of logics are mostly depending on these properties - .Rest of the paper is organized as follows: Session-2 discuss about overview of logic styles necessary for design, the design of three input XOR is explained in Session-3 and Session-4 mention the simulation setup and result discussion, finally in Session-5 conclude the paper.
with higher complication forces us to enhance the performance, area, efficiency and practicality of arithmetic logic circuits. Several efforts are targeted on the development of adder styles . Since the utilization of carry look-ahead principle for high-speed arithmetic units, one in all, the challenges in VLSI processor style these days is structured for constructing CLA circuits, exactly for the 8-bit circuits while not limiting the purposeful flexibility. A coffee power high performance FTL circuit technique is projected in  for reducing power dissipation and decreasing propagation delay in domino logic. The low power FTL dynamic logic is achieved with the help of feed through dynamic CMOS logic structure . Wang, Tsai  used the 8-bit CLA victimization- the dual-Vt domino logic blocks that are organized in a very PLA- like manner and synchronously triggered. It is enforced on chemical element to verify the facility reduction also because of the preservation of high speeds . Proposed an 8-bit pipelined CLA victimization- the dual- Green Mountain State domino logic blocks to scale back the facility dissipation. Dual-Vt Domino Logic Circuits foreseen for reducing sub-threshold discharge current in domino logic circuits is projected in . Sleep switch twin threshold voltage domino logic with reduced sub-threshold logic gate compound discharge current is projected and tried in . The high speed arithmetic circuit obtained victimization FTL logic in . Normally, domino CMOS logic is widely employed in high performance integrated circuits. It reduces the device count and chemical element space, and improves performance in comparison to the quality totally complementary static CMOS logic .
In this paper, the proposed high-voltage drivers are based on stacked low-voltage standard CMOS transistors and are technology independent. Their disadvantage however, is that depending on the number of stacked transistors, switching speed may not satisfy requirements because of raised on- resistance of the pull-up and pull-down driver transistors, re- sulting in slower charge and discharge characteristics of ca- pacitive output nodes.
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In this paper, various CMOS level shifter circuits have been compared in terms of voltage shifting levels, power dissipation and delay. The simulation results show that the Wilson current mirror based level shifter design is better than other conventional level shifter designs. The wilson current mirror based level shifter shifts 0.3V to 1.1V during the preliminary analysis. The power dissipation and propagation delay of wilson current mirror based level shifter obtained during the preliminary analysis is 50.2 pW and 265 pS, respectively. The conventional dual current mirror based level shifter design is the worst, because it is in development stage. The conventional dual current mirror based level shifter shifts 0.3V to 0.7V during the preliminary analysis. The power dissipation and propagation delay of conventional dual current mirror based level shifter obtained during the preliminary analysis is 7.55 uW and 5.1 nS, respectively. Currently, the researchers are focusing on dual current mirror based level shifter designs to optimize the power dissipation.