deep sub-micron technology
Characterization of 9T SRAM Cell at Various Process Corners at Deep Sub-micron Technology for Multimedia Applications
... the technology scaling has also made it even more challenging to maintain a sufficient cell stability margin while keeping the same scaling pace of access time and cell size as the mismatching of threshold voltage ...
5
Design of Two Stage Operational Amplifier with High Gain and High CMRR in Deep Sub-Micron Technology
... With the advancement in VLSI technology Digital Signal Processing has become more reliable and popular in almost all electronic applications. Digital systems have enormous advantages over analog systems like ...
10
Characterization of PNN Stack SRAM Cell at Deep Sub Micron Technology with High Stability and Low Leakage for Multimedia Applications
... CMOS technology down to 50 nm technology [1, ...the technology scaling, accurate estimation of SRAM data storage stability in pre-silicon design stage and verification of SRAM stability in the ...
5
Minimization Leakage Current of Full Adder Using Deep Sub-Micron CMOS Technique
... current deep-sub micron technology with low threshold voltages, sub threshold and gate leakage have become dominant sources of leakage and are expected to increase with the ...
7
Analysis of Different Types of Domino Logic: A Review
... In deep sub-micron technology the Leakage current associated with that Design is quite significant therefore there is a need of strong keeper that will compensate for the loss of charge[2], ...
8
Area- and energy-efficient CORDIC accelerators in deep sub-micron CMOS technologies
... in deep sub-micron CMOS tech- nologies at very low area and energy costs and are attrac- tive to be used as hardware accelerators for Application Spe- cific Instruction Processors ...
7
Design and Implementation of Sub Micron Level 10T Full Adder in ALU Using Cell Based and SOC Technology
... cmos technology, in short design of ALU can be a better ...dissipation. Deep submicron full adder can be used in encryption algorithm for security ...
6
Characterization of a Novel Low Power SRAM Bit Cell Structure at Deep Sub Micron CMOS Technology for Multimedia Applications
... memory sub-cells, the write sub-cell (Pull Down Transistors: N0, N1; Access Transistors: N2, N3; Pull up Transistors: P0, P1) and the read-sub cell (Read Access Transistors: N4, N5; and a Gated pMOS ...
6
Design of VCOs in Deep Sub-micron Technologies
... nm technology with 0.85 V supply, and likely other advanced-scaled deep sub- micron CMOS technologies at a similar frequency, a varactor-tuned ring oscillator may be preferred over LDO-tuned ...
92
Survey and Evaluation of D Flipflop for Low Power Counter Design Using Sub-Micron Technology
... Today LFSR’s are present in nearly every coding scheme as they produce sequences with good statistical properties, and they can be easily analysed. Moreover they have a low-cost realization in hardware. Counters such as ...
5
Analysis of Capacitance Across Interconnects of Low-K Dielectric Used in a Deep Sub-Micron CMOS Technology
... exploit deep submicron (DSM) technologies to design faster and smaller circuits, we must revisit the problem of calculating the gate propagation ...contact technology severely degrade the device ...
8
Dynamics and Statics of Liquid-Liquid and Gas-Liquid interfaces on Non-Uniform Substrates at the Micron and Sub-Micron Scales
... We observed highly transient bubble migration phenomena in the asymptotic limit of zero Capillary and Bond numbers that is only observable at sub-micron scales and proposed a model to explain the main ...
176
Sub-micron PMOS transistor using electron beam lithography
... small very looking the at on modulation Length effect a with effects of way look to explained is there second is magnitude the by made A drain the with channel be can though Channel Chan[r] ...
118
Disproportionate Effect of Sub-Micron Topography on Osteoconductive Capability of Titanium
... Ten-week-old male Sprague–Dawley rats were anesthetized by inhalation of 1%–2% isoflurane. Only left femurs were used to receive an implant. The left leg area was shaved and scrubbed with 10% povidone-iodine solution. ...
16
Low-Power Adder Design for Nano-Scale CMOS
... consumption at deep submicron because it uses an inverter. In inverter, there is a direct path between power supply and ground with only two transistors. Therefore, inverter is one of the high static power ...
5
Micromagnetic study of the vortex state in sub-micron iron discs
... of sub-micron iron discs are performed for different normalized inter-dot distance (distance/diameter), to better understand the magnetic behaviour of these nanos- ...
6
Sub-Micron Plasmonic Waveguide for Efficient Sensing of Bio-Fluids
... This way the change in the guided mode intensity along the direction of propagation is redistributed due to localization and the device becomes more sensitive to the change in permittivi[r] ...
12
Unveiling the multi-step solubilization mechanism of sub-micron size vesicles by detergents
... In summary, we have directly monitored the solubilization of sub-micron size lipid vesicles that cannot be resolved using conventional optical techniques in response to TX-100 using svFRET, FCS and QCM-D. ...
11
Development and characterization of a sub-micron CMOS process as an educational tool at RIT
... go athena # RIT Submicron Process Simulation n-well formation # Set up a mesh suitable for SubMicron CMOS line x loc=0 spac=0.1 line x loc=10.0 spac=0.1 # line y loc=0.00 spac=0.005 line[r] ...
218
Single Step Assembly of Biomolecule-Loaded Sub-Micron Polysulfone Fibres
... Creatinine is slightly soluble in DMSO and 5 based on the Hansen solubility parameters, the distance for DMSO, Ds-p =8.5 MPa1/2 is 6 less than the radius of interaction R< 9.40 of PSU Ta[r] ...
25