direct form FIR architecture
A Reconfigurable FIR Filter Architecture of FIR Filter Performance for Dynamic Power Consumption
5
Design of Transpose Form Block Fir Filter for Reconfigurable Applications
8
Design of an Adaptive Filtering Algorithm for Noise Cancellation
6
Comparison of Power and Area in High Performance Fir Filter Architecture for Fixed and Reconfigurable Application
7
Configurable Fir Filter Using Different Multiplier Technique
6
Design of Area Efficient FIR Filter Architecture for Fixed and Reconfigurable Applications
8
Synthesis of Low-Power Area Efficient Constant Multiplier Architecture for Reconfigurable Fir Filter Using Hybrid Form
7
Delay Efficient Fir Filter Architecture for Fixed And Re-Configurable Applications
8
A High Speed hybrid FIR Filter Architecture for Fixed and Reconfigurable Applications
5
MCM Based FIR Filter Architecture for High Performance
6
An Efficient VLSI Architecture for FIR Filter using Computation Sharing Multiplier
6
Block Fir Filters in Transpose Form Configuration for Area Delay Efficient Realization of both Fixed and Reconfigurable Applications
6
Blind Deconvolution in Nonminimum Phase Systems Using Cascade Structure
10
A High Speed FIR Filter Architecture Based on Higher Radix Algorithm
7
FPGA Implementation of Ultra-High Speed and Configurable Architecture of Direct/Inverse Discrete Wavelet Packet Transform Using Shared Parallel FIR Filters
12
A VHDL Implementation of Direct, Pipelined and Distributed Arithmetic FIR Filters
5
A locally-biased form of the direct algorithm
10
Incorporation of Reduced Full Adder and Half Adder into Wallace Multiplier and Improved Carry Save Adder for Digital FIR Filter
9
Finite impulse response filter design on distributed arithmetic architecture
17
Various Reduction Techniques for Parallel FIR Digital Filter Using Parallel Architecture
5