drain-source on-resistance
Silicon N-Channel Power MOSFET CS140N08 AR
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Influence of Extended Bias Stress on the Electrical Parameters of Mixed Oxide Thin Film Transistors
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PHYSICAL-TECHNOLOGICAL ASPECTS OF A MULTIFUNCTIONAL SENSOR BASED ON A FIELD-EFFECT TRANSISTOR
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MTD3055VT4. MAXIMUM RATINGS (T C = 25 C unless otherwise noted) MARKING DIAGRAMS ORDERING INFORMATION. R DS(on) TYP 60 V 100 m
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The investigation on the factors that affect the resistance of drain to source in semiconductor packaging
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Design And Characterization Of 20NM SOI MOSFET Doping Abruptness Dependent
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Static and dynamic TSEPs of SiC and GaN transistors
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Analysis on Effective parameters influencing Channel Length Modulation Index in MOS
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Modeling of the Transfer Characteristics for High Series Resistance in Nanoscale FD SOI MOSFET Devices
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Numerical Optimization for Source-Drain Channel Resistance of AlGaN/GaN HEMTS
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Source. Gate N+ N+ N+ Drain. Figure 1 Structure of D Series (Vertical type) (N channel) Channel. Source. Drain. Gate N N+ N+ P+ Substrate
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Predicted Performance Advantages of Carbon Nanotube Transistors with Doped Nanotubes as Source/Drain
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← Return to Article Details Assessment of Post Exposure Prophylaxis (PEP) in Omdurman Voluntary Counselling and Testing Center (OVCTC) Download
14
Advanced Source Injector for N-type Enhancement-Mode GaN based Schottky Barrier MOSFET with Source/Drain Extension
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Design of Common-Source/Drain Active Balun Using 90nm CMOS Technology
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Improving catchment discharge predictions by inferring flow route contributions from a nested scale monitoring and model setup
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5.11 THE JUNCTION FIELD-EFFECT TRANSISTOR (JFET)
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Gate-to-channel parasitic capacitance minimization and source-drain leakage evaluation in germanium PMOS
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Bias dependent photoresponsivity of multi layer MoS2 phototransistors
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Learning by resistance: An analysis of resistance to change as a source of organizational learning
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