efficient architecture
An Energy Efficient Architecture of IoT based on Service Oriented Architecture (SOA)
... primary leaders for the advance development of IoT [6]. The cachet and gesture of an article can be detected with the help of sensor (like RFID) in special condition [7]. For example, take a container, with the help of ...
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Efficient Architecture for QoS Providence across WiMAX
... managements architecture with addition of bandwidth allocation algorithm at base ...proposed architecture, when a connection request is forwarded to Base Station the CAC policy checks whether it has ...
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Efficient Architecture and Implementation for NTRU Based Systems
... RSA and elliptic curve cryptosystem (ECC) are two currently popular public key systems in modern cryptography. All these asymmetrical key systems are based on some hard mathematical problems. In another word, breaking an ...
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Implementation on FPGA Area-Delay Efficient Architecture of CSLA
... operation. Architecture of CSLA, there is chance to reduce area & delay which is based on sum generation unit and carry generation ...CSLA architecture have been implemented on FPGA and compared result ...
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An Efficient Architecture for PCI Bus Design
... PCI bus is widely used in embedded applications for data transmission in burst mode. The architecture of the PCI bus is shown in Figure 1. PCI Bridge connects to the I/O devices as well as to the bus controller. ...
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An Efficient Architecture in Next Generation Wireless Networks
... select architecture from suggested schemes, which reduces signalling traffic loads in international roaming situation [1], ...an efficient and effective scheme which reduces the overhead of tracing and ...
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An efficient interpolation filter VLSI architecture for HEVC standard
... signing efficient architecture for HEVC MC interpola- tions ...filter architecture with a prediction unit (PU)-adaptive filtering flow and a unified filter combin- ing the eight-tap luma and four-tap ...
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Exploiting the Reconfigurability of Programmable Hardware for Neural Engineering
... area-efficient architecture for a leaky membrane, and compact implementation of neural cell which can be used for emulating large scale fully parallel spiking neural ...
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Area and power efficient DCT architecture for image compression
... transformation matrix, which requires only 12 addi- tions, thus avoiding the need for multiplication and bit shift operations. The proposed approximation DCT for image compression is a simple, efficient ...
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Power Efficient Survivor Memory Architecture for Viterbi Decoder
... the architecture shown in ...the architecture above brings huge power consumption due to the interchanging of contents in every register, just like the RE ...power efficient architecture for ...
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THE APPLICATION OF M-LEARNING IN IMPROVING SPEAKING SKILLS AMONG EFL LEARNERS.
... based architecture for FIB Lookup using 2-phase BF: It is a new FIB lookup architecture [25] that works on the concept of Longest Prefix Trie (LPT) which is an efficient longest prefix matching data ...
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Power Efficient Parallel Chien Search Architecture Using a Two-Step Approach in Rs Codes
... [4] Y. Lee, H. Yoo, and I.-C. Park, ―Highthroughput and low-complexity BCH decoding architecture for solid-state drives,‖ International Journal of Research Available at https://edupediapublications.org/journals ...
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An Efficient VLSI-EDDR Architecture for Motion Estimation in Testing Applications
... IV. PROPOSED VLSI-EDDR ARCHITECTURE Fig. 2 shows the conceptual view of the proposed EDDR scheme, which comprises two major circuit designs, i.e. error detection circuit (EDC) and data recovery circuit (DRC), to ...
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Memory-Reduced and Area Efficient Turbo Decoding Architecture
... ABSTRACT: A new compression technique known as Next Iteration Initialization (NII) metrics is proposed for modifying the storage demands of turbo decoders. The proposed method stores only the range of state metrics with ...
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An Efficient, Low Power 256X8 T-SRAM Architecture
... High-speed lookup operations are performed by Ternary Content addressable memories. But TCAMs are limited due to low storage density, relatively access time, low scalability, complex circuitry, and are very expensive in ...
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VHDL Design of Efficient Router Architecture for Network-on-Chip
... ABSTRACT: Network-on-Chip (NoC) is a new research in the direction of communication network into System-on- Chip (SoC). Problems of traditional bus-based SoC can be solved and it will give the better communication ...
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HIGH SPEED AND LOWER HARDWARE COMPLEXITY VLSI ARCHITECTURE FOR LIFTING BASED DISCRETE WAVELET TRANSFORM
... transform architecture has been ...Folded architecture method has been adopted. In the proposed architecture, modifications are made to the lifting scheme, and the intermediate results are combined ...
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An Efficient VLSI Architecture of a Clock-gating Turbo Decoder
... This motivates the employment of the lookup table based algorithms in energy-constrained scenarios, since it approximates the optimal Log more closely than the Max-Log [9] and therefore does not suffer from the ...
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Energy-Efficient Distributed Processing in Vehicular Cloud Architecture
... End users are growing more dependent on cloud services and data centers [1]. As the demand on cloud services grows higher, the data centers, as expected, tend to grow even bigger and more expensive in term of both ...
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A MODERN SELF QUANTIZING TECHNIQUE ARCHITECTURES USING DISCRETE WAVELET TRANSFORM FOR IMAGE PROCESSING APPLICATIONS
... This paper exists Precision-Aware approaches and related hardware implementations for performing the operation of DWT. It includes implementation of BP architecture and DS design methodologies. These methodologies ...
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