• No results found

high-frequency clock signal

Time Frequency System Builds and  Timing Strategy Research of VHF  Band Antenna Array

Time Frequency System Builds and Timing Strategy Research of VHF Band Antenna Array

... (Very High Frequency) band antenna array will receive analog signal from universe for sto- rage after digital sampling and adding time scale, and then do the interference analysis of differ- ent ...

10

Rotary Clock based High-Frequency ASIC Design Methodology

Rotary Clock based High-Frequency ASIC Design Methodology

... the clock distribution network is routed before data signal nets in order to ensure high clock skew ...rotary clock based designs, there are multiple clock phase ...two ...

115

Switching Reduction in CMOS Circuits using Multistage  Clock Network

Switching Reduction in CMOS Circuits using Multistage Clock Network

... quite high for only two ...very high clock frequencies, as the data- to-q delay must be less than half the input clock period minus some picoseconds taking clock jitter and duty cycle ...

7

Design of a Low Frequency RFID Reader

Design of a Low Frequency RFID Reader

... demodulated signal, is then coded clock needs to be ...the high end of a ...the signal. The threshold between a high and a low signal is determined by finding the halfway point ...

6

A low complexity digital frequency calibration with high jitter immunity for ultra-low-power oscillators

A low complexity digital frequency calibration with high jitter immunity for ultra-low-power oscillators

... digital frequency calibration method has been designed and evaluated using synthesized hardware descrip- tion language on an Virtex-5 FPGA ...low frequency digitally controlled oscillator (DCO) on a sepa- ...

6

A Review on Clock Skew Compensation Techniques

A Review on Clock Skew Compensation Techniques

... reference signal or the standard ...oscillation frequency and phase of internal oscillator so that they match the frequency and phase of a reference signal and the regulation of delay range in ...

5

High Speed Direct Signal Frequency Synthesizer

High Speed Direct Signal Frequency Synthesizer

... output signal with two samples for each ...resulting signal frequency is ½ times of clock signal frequency (In practical conditions more that ...of clock signal ...

5

16-Bit, 250 ksps CMOS ADC AD7664. Type/kSPS Pseudo AD7660 AD7650

16-Bit, 250 ksps CMOS ADC AD7664. Type/kSPS Pseudo AD7660 AD7650

... BUSY signal goes HIGH until the completion of the ...digital signal, it should be designed with special care with fast, clean edges, and levels with minimum overshoot and undershoot or ...CNVST ...

24

Experimental investigation of high speed digital circuit’s return current on electromagnetic emission

Experimental investigation of high speed digital circuit’s return current on electromagnetic emission

... or signal and return current path of the circuit and the employment of trace termination on radiated emission ...for high-speed digital circuit PCB layout that operates at various frequencies are presented ...

5

Symbol Recovery Circuit design for deep-space MARS receiver using SOI technology

Symbol Recovery Circuit design for deep-space MARS receiver using SOI technology

... The frequency estimator circuit keeps track of the number of times there are edges when the Inc (or up) signal of the PFD is high and the duration for which the Dec (or down) signal are ...

105

Signal generation and processing in high-frequency / high-speed silicon-based integrated circuits

Signal generation and processing in high-frequency / high-speed silicon-based integrated circuits

... optical signal is detected by a PIN or avalanche photodiode (direct- detection), and the electrical signal is then amplified by a transimpedance amplifier (TIA), followed by a clock-and-data-recovery ...

142

Online Full Text

Online Full Text

... as clock recovery, data retiming, frequency translation and clock smoothing ...output signal from a given PLL suffers from an associated jitter especially at high bit rate resulting in ...

5

DESIGN AND CONSTRUCTION OF THE FREQUENCY DIVIDER USING 7490 DECADE COUNTER

DESIGN AND CONSTRUCTION OF THE FREQUENCY DIVIDER USING 7490 DECADE COUNTER

... The 74LS90 integrated circuit is basically a MOD-10 decade counter that produces a BCD output code. The 74LS90 consists of four master-slave JK flip-flops internally connected to provide a MOD-2 (count-to-2) counter and ...

5

Canopy T1/E1 Multiplexer. User Guide. T1E1Mux-UG-en Issue 3 September 2004

Canopy T1/E1 Multiplexer. User Guide. T1E1Mux-UG-en Issue 3 September 2004

... The clock for a T1/E1 circuit is normally derived from the incoming T1/E1 ...A clock in a telecommunications system or network has a quality level or stratum number assigned to ...

73

Research on Multipoint Positioning Based on TOA Cooperate with AOA Location Algorithm

Research on Multipoint Positioning Based on TOA Cooperate with AOA Location Algorithm

... a high temporal ...pulse signal. The duration of the pulse signal in time domain is extremely ...UWB signal is ...UWB signal belongs high- frequency signal, it is ...

6

Transmission Characteristics of High Frequency Signal in Low Voltage Power Lines

Transmission Characteristics of High Frequency Signal in Low Voltage Power Lines

... resonant signal generation, resulting in low voltage power line high frequency signal attenuation is very complex, seriously affects the quality of carrier ...The high frequency ...

6

Performance Monitor Based Power Management for big.little Platforms

Performance Monitor Based Power Management for big.little Platforms

... lower clock frequency would be ...a clock frequency below the core transition limit (800 MHz) is used which allows the system to execute on the LITTLE A7 ...

6

The Key Technology Design of the Real-Time Monitoring System Based on FPGA

The Key Technology Design of the Real-Time Monitoring System Based on FPGA

... analog signal from the sensor and convert it into digital signal which can be recognized and addressed by the computer, calculate and process the signal corre- spondingly according to different needs ...

9

AN OPTIMIZATION OF A COMMUNICATION SYSTEM USING PULSE TRIGGERING METHOD

AN OPTIMIZATION OF A COMMUNICATION SYSTEM USING PULSE TRIGGERING METHOD

... for high-speed serial information ...a high-speed Serializer (Parallel-in Serial-out 10-bit Shift ...The high-speed Deserializer (Serial-in Parallel-out 10-bit Shift Register) on the receiver aspect ...

8

Lead Acid Battery Analysis using S-Transform

Lead Acid Battery Analysis using S-Transform

... original signal phase, as well as the capability to detect the lossless inverse transformation, compared to WT ...and frequency, ST can also be applied in PQ disturbance application ...

8

Show all 10000 documents...

Related subjects