low-temperature gate dielectrics
Reactions of High-k Gate Dielectrics: Studies in Hafnium, Zirconium, Yttrium, and Lanthanum-based Dielectrics and in-situ Infrared Results for Hafnium Dioxide Atomic Layer Deposition
... Y-silicate dielectrics in contrast to ZrO 2 and Al 2 O 3 ...Very low resistivity Ru and rutile stoichiometric RuO 2 films, deposited via reactive sputtering, were evaluated as gate electrodes on ...
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Optimization of nitrided gate dielectrics by plasma-assisted and rapid thermal processing
... tinuous random network structures with low bulk defect den- sities, primarily because of their high H-atom content ~; 30 at. % ! ; ~ iii ! these films contain several kinds of bonded H: ~ a ! in nearest-neighbor ...
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Investigation of MOS Interfaces with Atomic-Layer-Deposited High-k Gate Dielectrics on III-V Semiconductors.
... Metal-oxide-semiconductor field effect transistors (MOSFETs) using a high mobility GaAs channel are attractive candidates for future n-channel MOS transistors for logic applications. The performance of a GaAs MOSFET is ...
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GaN-dielectric interface formation for gate dielectrics and passivation layers using remote plasma processing
... reported low oxide fixed charge (and/or interface state density) in the range of 1 x 10 11 cm -2 or ...reported low values of interface trap densities are based on the high frequency C-V curves measured at ...
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Structural and electrical characteristics of high κ Er2O3 and Er2TiO5 gate dielectrics for a IGZO thin film transistors
... Amorphous indium-gallium-zinc-oxide (a-IGZO) thin- film transistors (TFTs) are being extensively explored as a replacement for amorphous and polycrystalline silicon TFTs in large-area display technologies, such as ...
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Transition from thermally grown gate dielectrics to deposited gate dielectrics for advanced silicon devices: A classification scheme based on bond ionicity
... a gate metal. This change is driven by issues: 共 i 兲 the high temperature process- ing required for dopant activation in polycrystalline Si and Si, Ge, and 共 ii 兲 the additional capacitance that is ...
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The performance and reliability of PMOSFET's with ultrathin silicon nitride/oxide stacked gate dielectrics with nitrided Si-SiO2 interfaces prepared by remote plasma enhanced CVD and post-deposition rapid thermal annealing
... into gate stack processing, with minimum modification of current process ...layer gate dielectrics made with oxides and nitrides, both deposited by RPECVD, and in the ...stack gate ...
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Tunneling currents through ultrathin oxide/nitride dual layer gate dielectrics for advanced microelectronic devices
... complementary metaloxide semiconductor device structures which require oxide equivalent thicknesses in the range from about 2 to 1.2 nm. The physical thicknesses of these films would typically be about one and a half ...
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Structural and electrical characterization of SiO2 gate dielectrics deposited from solutions at moderate temperatures in air
... (PECVD) in particular has often been used to lower film deposition temperatures. 4,11,12 However, the drawbacks to plasma processing include particle contamination as well as surface damage from the energetic plasma ...
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Suppression of boron transport out of p(+) polycrystalline silicon at polycrystalline silicon dielectric interfaces
... poly-Si gate electrodes de- posited by conventional CVD, and into the source and drain regions of the device structure at energy of 20 MeV to a level of 5 ⫻ 10 15 /cm 2 ...a low temperature CVD oxide ...
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The interfaces of lanthanum oxide based subnanometer EOT gate dielectrics
... the gate electrode material to be stable at the annealing ...the gate dielectric also. High-temperature post-implant annealing will also result in the growth of the interfacial layer at the high-k/Si ...
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Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications.
... The memory capacitor hysteresis window for a couple of different FG thickness conditions (35Å and 100Å) are shown in Fig. 5.22. While a wide memory window was observed (~4V) for both thickness conditions, the start of ...
247
Low series resistance structures for gate dielectrics with a high leakage current
... growth temperature of the gate oxide by atomic layer deposition ...the temperature inside the growth chamber of the ALD ...actual temperature of the wafer. The temperature is controlled ...
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Implementation of Low Power Arithmetic Circuits Using Reversible Gates
... Everyone in the world of modern circuit design tries to reduce the power consumption by the circuit. As demonstrated by R.Landauer in the early 1960s, irreversible hardware computation, regardless of its realization ...
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Temperature-stable dielectric properties from -20°C to 430°C in the system BaTiO3-Bi(Mg0.5Zr0.5)O3
... These temperature stable relaxor dielectrics are of interest for new types of high volumetric efficiency capacitors operating at > 200 ºC for use in electronic systems for aviation, automotive and ...
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Electrical Instability in Pentacene Transistors with Mylar and PMMA/Mylar Gate Dielectrics Transferred by Lamination Process
... of gate electrode named bias stress tends to shift the thre- shold voltage, degrades the subthreshold parameters [17] reducing the ...Under gate bias-stress, the drain current decreases with time due to ...
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A REVIEW ON DOUBLE GATE MOSFET
... by gate oxide of same thickness or different depending upon ...increases gate coupling thus gate control over the channel ...single gate except it has two ...
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Characterization of Wide Band Gap Power Semiconductor Devices.
... between gate and source, all the electrons are ...the gate is created relative to drift region. Once gate is reached to threshold voltage, there are enough electrons to conduct current in reverse ...
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Electron mobility in MOSFETs with ultrathin RTCVD silicon nitride/oxynitride stacked gate dielectrics
... The effective electron mobility for oxynitride/nitride stacked gate dielectrics has been examined. The mobility is shown to be degraded by coulombic scattering from interface charges and bulk dielectric ...
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Separate and independent reductions in direct tunneling in oxide/nitride stacks with monolayer interface nitridation associated with the (i) interface nitridation and (ii) increased physical thickness
... Stacked dielectric layers have been prepared by 300 °C remote plasma processing, including; 共 i 兲 interface formation and monolayer interface nitridation, 12,13 followed by 共 ii 兲 re- mote plasma-assisted deposition of ...
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