networks on a chip
VULCAN integrates ChIP-seq with patient-derived co-expression networks to identify GRHL2 as a key co-regulator of ERa at enhancers in breast cancer
... VULCAN applies gene set enrichment analysis [16] to identify enrichment of our mutual information network derived regulons in differential ChIP-seq data. To validate our method, we compared the results of VULCAN ...
17
Reliability-aware multi-segmented bus architecture for photonic networks-on-chip
... photonic links. 3-D integration, for example, involves stacking multiple layers of circuitry. This results in more interconnections, as each core has another axis along which to link. The stacked cores allow for shorter ...
45
A Review of Optical Routers in Photonic Networks-on-Chip: A Literature Survey
... Optical routers play an important role in the ONoC chip. Due to this important role, different types of routers are designed and implemented. Optical network-on-chip that is considered in recent years, ...
12
Cost-aware Topology Customization of Mesh-based Networks-on-Chip
... Abstract: The small world network idea recently has been introduced in order to optimize the performance of the Networks-on-chip. Based on this method the architecture will be neither fully customized nor ...
8
Topology Re Configuration for On Chip Networks with Back Tracking
... Optimizing the network topology and core to network mapping are two important application-specific NoC customization methods which affect the network’s performance and related characteristics such as average inter- core ...
6
Fast simulation of networks-on-chip with priority-preemptive arbitration
... on- chip interconnects. In the case of complex interconnects like Networks-on-Chip (NoCs), cycle- accurate simulation of a few seconds of the system’s execution can take hours [Genko et ...
21
Packet switched on chip FPGA overlay networks
... Network-on-Chip As VLSI capacities increased, it became possible to pack multiple functional elements onto a single chip. These functional elements were originally discrete chips on circuit boards that were ...
91
Time-multiplexed FPGA overlay networks on chip
... One model that is particularly intriguing to NoC designers desiring flexibility is the Field Pro- grammable Gate Array (FPGA). FPGAs provide a general reconfigurable fabric of logic upon which arbitrary digital hardware ...
106
Least Upper Delay Bound for VBR Flows in Networks on Chip with Virtual Channels
... switched networks we consider worst-case delay bounds for Variable Bit-Rate (VBR) flows with aggregate scheduling, which schedules multiple flows as an aggregate ...
41
Low cost fault tolerant routing algorithm for Networks on Chip
... Junxiu Liu received a BEng in Electronic Information Engineering from Hunan Institute of Science and Technology in 2007 and an MPhil in Signal and Information Processing from Guangdong University of Technology in 2010. ...
35
Effective Routing Algorithm and Topology on Power Consumption in Networks on Chip
... Routers in NoCs route the data according to routing algorithm. Routing algorithms are divided into three groups; deterministic, partially adaptive and fully adaptive. The problems on routing occur when the packets cannot ...
8
Least Upper Delay Bound for VBR Flows in Networks-on- Chip with Virtual Channels
... switched networks we consider worst-case delay bounds for Variable Bit-Rate (VBR) flows with aggregate scheduling, which schedules multiple flows as an aggregate ...
34
A Fault Injection Framework for Reliability Evaluation of Networks on Chip Designed for Space Applications
... With the increasing complexity of circuits and decreasing feature sizes, it is becoming extremely difficult to manufacture fault-free circuits. Also, with the decreasing feature size comes a higher susceptibility to ...
111
Single-photon electroluminescence for on-chip quantum networks
... An electrically driven single-photon source has been monolithically integrated with nano-photonic cir- cuitry. Electroluminescent emission from a single InAs/GaAs quantum dot (QD) is channelled through a suspended ...
5
Chip Discrimination for UWB Impulse Radio Networks in Multipath Channels
... The chip discriminator and the maximal ratio combining (MRC) RAKE receiver require accurate channel estimates and performance suffers accordingly when im- perfect channel parameters are ...the ...
92
TPSS: A Flexible Hardware Support for Unicast and Multicast on Networks-on-Chip
... Abstract—Multicast is an important traffic mode that runs on multi-core systems, and an efficient hardware support for multicast can greatly improve the performance of the whole system. Most multicast solutions use the ...
10
Communication-centric debug of systems-on-chip using networks-on-chip
... Network-on-chip introduces new possibilities for debugging systems-on-chip. Debug is nec- essary because first-time-right SoC designs are still an utopia. An increasing number of cores and components within ...
62
Virtual Circuit-Switched Sheme for On-Chip Networks
... ABSTRACT: Network-on-chip (NoC) has emerged as a scalable and promising solution to global communications within large multi core systems. The NoC with virtual point-to-point connections (VIP)is the existing, the ...
7
Performance evaluation of single- and multi-hop wireless networks-on-chip with NAS Parallel Benchmarks
... According to Ganguly et al. [17], if some or all wired connections in a NoC are replaced with wireless high- bandwidth single-hop connections, there will be a reduc- tion in energy dissipation and latency, since these ...
16
HDLC Implementation in Wireless Sensor Networks
... The work aims the designing and implementing an efficient HDLC chip. We use pipelining technique in HDLC register module which increases the throughput of the system and also helps in decreasing the delay of the ...
5