Networks on Chip
Low cost fault tolerant routing algorithm for Networks on Chip
... Junxiu Liu received a BEng in Electronic Information Engineering from Hunan Institute of Science and Technology in 2007 and an MPhil in Signal and Information Processing from Guangdong University of Technology in 2010. ...
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Fast simulation of networks-on-chip with priority-preemptive arbitration
... on- chip interconnects. In the case of complex interconnects like Networks-on-Chip (NoCs), cycle- accurate simulation of a few seconds of the system’s execution can take hours [Genko et ...
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Cost-aware Topology Customization of Mesh-based Networks-on-Chip
... the Networks-on-Chip (NoC) paradigm has emerged as a promising solution to on-chip communication challenges within the silicon- based electronics ...
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A Fault Injection Framework for Reliability Evaluation of Networks on Chip Designed for Space Applications
... With the increasing complexity of circuits and decreasing feature sizes, it is becoming extremely difficult to manufacture fault-free circuits. Also, with the decreasing feature size comes a higher susceptibility to ...
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A Review of Optical Routers in Photonic Networks-on-Chip: A Literature Survey
... Optical routers play an important role in the ONoC chip. Due to this important role, different types of routers are designed and implemented. Optical network-on-chip that is considered in recent years, ...
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Communication-centric debug of systems-on-chip using networks-on-chip
... The Quality of Service (QoS) offered by a network-on-chip is of great importance, however services also have their costs in terms of speed, area and power consumption [20]. Æthereal, Philips’ ...
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TPSS: A Flexible Hardware Support for Unicast and Multicast on Networks-on-Chip
... Abstract—Multicast is an important traffic mode that runs on multi-core systems, and an efficient hardware support for multicast can greatly improve the performance of the whole system. Most multicast solutions use the ...
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Effective Routing Algorithm and Topology on Power Consumption in Networks on Chip
... Abstract: Network on Chip (NoC) is used as an appropriate solution to solve the communication problems in System on Chip (SoC). Due to the advanced VLSI technology the power consumption has become a major ...
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Reliability-aware multi-segmented bus architecture for photonic networks-on-chip
... Photonic networks also only need to have photonic switches turn on once per message, as opposed to once per bit like electronic network, which makes energy dissipation independent from bit rate, further decreasing ...
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Least Upper Delay Bound for VBR Flows in Networks on Chip with Virtual Channels
... In this work, we have derived the analysis procedure to investigate per-flow delay bound. To this end, we have given theorems to calculate end-to-end ESC and internal output arrival curves in a FIFO multiplexing network. ...
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Least Upper Delay Bound for VBR Flows in Networks-on- Chip with Virtual Channels
... The proposed models by Lee [2003 ] and Rahmati et al. [2009 ; 2013 ] are inspired by schedulability analysis. Lee [2003 ] presents a worst-case analysis model for real- time communication and also proposes a feasibility ...
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Performance evaluation of single- and multi-hop wireless networks-on-chip with NAS Parallel Benchmarks
... Figure 3 allows us to infer, from the high percentage of unicast packets sent for the CG workload, that point-to- point communications are dominant. Even though the figure shows that, for networks with eight or ...
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Time-multiplexed FPGA overlay networks on chip
... One model that is particularly intriguing to NoC designers desiring flexibility is the Field Pro- grammable Gate Array (FPGA). FPGAs provide a general reconfigurable fabric of logic upon which arbitrary digital hardware ...
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Topology Re Configuration for On Chip Networks with Back Tracking
... for networks-on-chip (NoC) on which arbitrary application-specific topologies can be implemented with backtracking which provides guaranteed throughput is ...
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Profiling gene promoter occupancy of Sox2 in two phenotypically distinct breast cancer cell subsets using chromatin immunoprecipitation and genome wide promoter microarrays
... and ChIP-PCR ChIP-chip was performed based on a previously de- scribed ChIP-PCR protocol ...[31]. ChIP-PCR was performed as previously described [18]. ChIP input DNA was run on ...
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Coupled Chip-to-Chip Interconnect Design
... AC coupled interconnect (ACCI) has been demonstrated as a systematic solution for providing higher pin density, smaller transceiver design and lower power dissipation for high speed chip-to-chip ...
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Organ-on-Chip In Development:Towards a roadmap for Organs-on-Chip
... A common perception of the interviewed experts is that the lay public easily grasps the core concept of OoC technology, and tends to get quickly excited about the potential to decrease or even replace animal testing. ...
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Comprehensive Review on Wireless Sensor Networks
... Often, the utility of a sensor network will rely on its ability to accurately and automatically locate each sensor in the network. A sensor network designed to locate faults will need accurate location information in ...
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Automatic Water Pollution Control and Filtration System for Rivers Using IOT
... Marco Zennaro, Athanasios Floros, GokhanDogan, Tao Sun, Zhichao Cao, Chen Huang, ManzoorBahader, Herve’ Ntareme et al.[9] proposed the design of a water quality monitoring system and, building upon the SunSPOT ...
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VULCAN integrates ChIP-seq with patient-derived co-expression networks to identify GRHL2 as a key co-regulator of ERa at enhancers in breast cancer
... ChIP-seq enables the identification of potential site-specific interactions at common binding sites be- tween transcription factors and their cofactors; however, to fully characterize all potential cofactors of a ...
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