Networks on Chip (NoC)
Realistic Workload Characterization and Analysis for Networks-on-Chip Design
... As silicon device scaling trends have simultaneously increased transistor density while reducing component costs, architectures incorporating multiple communicat- ing components are becoming more common. In these ...
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Per-Packet Global Congestion Estimation for Fast Packet Delivery in Networks-on-Chip
... Abstract Networks-on-chip (NOCs) are becoming the de facto communica- tion fabric to connect cores and cache banks in chip multiprocessors ...
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Cost-aware Topology Customization of Mesh-based Networks-on-Chip
... the Networks-on-Chip (NoC) paradigm has emerged as a promising solution to on-chip communication challenges within the silicon- based electronics ...
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Fast simulation of networks-on-chip with priority-preemptive arbitration
... on- chip interconnects. In the case of complex interconnects like Networks-on-Chip (NoCs), cycle- accurate simulation of a few seconds of the system’s execution can take hours [Genko et ...
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A Fault Injection Framework for Reliability Evaluation of Networks on Chip Designed for Space Applications
... With the increasing complexity of circuits and decreasing feature sizes, it is becoming extremely difficult to manufacture fault-free circuits. Also, with the decreasing feature size comes a higher susceptibility to ...
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Regional Congestion Awareness for Load Balance in Networks-on-Chip
... Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiproces- sors and system-on-chip ...interconnection networks use either oblivious ...
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A Design Methodology for Application-Specific Networks-on-Chip
... application-specific networks- on-chip (ASNoC) and its design ...mesh networks-on-chip are compared in performance, power, and area in ...
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Low cost fault tolerant routing algorithm for Networks on Chip
... Junxiu Liu received a BEng in Electronic Information Engineering from Hunan Institute of Science and Technology in 2007 and an MPhil in Signal and Information Processing from Guangdong University of Technology in 2010. ...
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Reliability-aware multi-segmented bus architecture for photonic networks-on-chip
... single chip, allowing for a structured, scalable system when compared to traditional on-chip ...communications networks in which information is transmitted in the form of optical ...
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Performance evaluation of single- and multi-hop wireless networks-on-chip with NAS Parallel Benchmarks
... According to Ganguly et al. [17], if some or all wired connections in a NoC are replaced with wireless high- bandwidth single-hop connections, there will be a reduc- tion in energy dissipation and latency, since these ...
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Effective Routing Algorithm and Topology on Power Consumption in Networks on Chip
... Topology determines the connection among the routers in NoCs. Some researchers present and analysis different topologies for NoCs. In [20], authors suggest a new NoC topology synthesis methodology to generate optimum ...
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TPSS: A Flexible Hardware Support for Unicast and Multicast on Networks-on-Chip
... Abstract—Multicast is an important traffic mode that runs on multi-core systems, and an efficient hardware support for multicast can greatly improve the performance of the whole system. Most multicast solutions use the ...
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Design of Networks-on-Chip for Real-Time Multi-Processor Systems-on-Chip
... The development of the T-CREST NOC will be based on the experiences from work on the MANGO and AEthereal NOC’s. As mentioned in the introduction, multi-processor platforms for embedded systems are typically optimized for ...
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GUARANTEEING THE QUALITY OF SERVICES IN NETWORKS ON CHIP
... An IP connected to a NOC may not always be able to accept incoming data. Assuming its input buffers are finite, several solutions are possible, with direct consequences for the service level that can offered. Packets ...
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Time-multiplexed FPGA overlay networks on chip
... single chip networks greatly exceed the maximum capacity of this device (32K ...our networks to large areas under the XC2V6000-4 cost model is ...single chip? In terms of current technology, ...
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Early Design Space Exploration of Hard Real-Time Embedded Networks-on-Chip
... Based on particular attributes such as the utilisation of task and message, task schedulability and the number of outgoing messages, the proposed algorithm could provide a schedulable ta[r] ...
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Least Upper Delay Bound for VBR Flows in Networks-on- Chip with Virtual Channels
... switched networks we consider worst-case delay bounds for Variable Bit-Rate (VBR) flows with aggregate scheduling, which schedules multiple flows as an aggregate ...
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Communication-centric debug of systems-on-chip using networks-on-chip
... The prediction of Gordon Moore in 1965 that the transistor density of semiconductor chips would double every 18 months still holds true. Designers can not keep pace with the increas- ing design complexity which results ...
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Least Upper Delay Bound for VBR Flows in Networks on Chip with Virtual Channels
... The proposed models by Lee [2003 ] and Rahmati et al. [2009 ; 2013 ] are inspired by schedulability analysis. Lee [2003 ] presents a worst-case analysis model for real- time communication and also proposes a feasibility ...
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SurfNoC: A Low Latency and Provably Non-Interfering Approach to Secure Networks-On-Chip
... As an optimization, we constrain our schedule such that two directions of the router propagate packets from the same domain at the same time. For example, the top-left router in Figure 2b propagates packets from domain 0 ...
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