Residue Number System

Abstract — Residue Number System (RNS) is a non-weighted number system for integer number arithmetic, which is based on the residues of a number to a certain set of numbers called module set. The main characteristics and advantage of residue number system is reducing carry propagation in calculations. The elimination of carry propagation leads to the possibility of maximizing parallel processing and reducing the delay. Residue number system is mostly fitted for calculations involving addition and multiplication. But some calculations and operations such as division, comparison between numbers, sign determination and overflow detection is complicated. In this paper a method for overflow detection is proposed for the special moduli set {2 n -1,2 n ,2 n +1}. This moduli set is favorable because

Over the centuries, information security has become a major issue. Encryption and decryption of data has recently been widely investigated and developed because there is a demand for a stronger encryption and decryption which is very hard for intrusion. Cryptography plays major roles in fulfilment of these demands. Many of researchers have proposed a lot of encryption and decryption algorithms. But most of the proposed algorithms encountered problems such as lack of reduced cost of data and error control mechanisms to maintain the security of data in the communication channel. In this paper, a highly secured data encryption and decryption scheme is proposed to enhance the Huffman‟s method. The Residue Number System (RNS) is employed with four moduli set {2 n-1 , 2 n ─1, 2 n

correct single error in a communication channel using redundant residue number system. Recently [6] Kati presented a residue arithmetic error correction scheme that was based on common factor using a moduli set. The work of [7] Mandelbaum was not left out in the area of error detection and correction using redundant residue number system, he also proposed a code to support other work in that area. The code theory approach of error detection and correction in RRNS was also proposed by (Sun and H. Kirshan) [8]. [9] Beckmann and Musicus design fault-tolerant convolution algorithm that is an extension of residue-number-system, the schemes applied to polynomial rings was described. The algorithm is suitable for implementation on multiprocessor systems and is able to concurrently mask processor failures. A fast algorithm based on long division for detecting and correcting multiple processor failures is presented in is work, a single fault detection and correction is studied, The coding scheme is capable of protecting over 90% of the computation involved in convolution. Goh and siddiqi design a multiple error correction and detection using redundant residue number system [10], [11] Tay and Chang design a new algorithm for the correction of single residue digit error in Redundant Residue Number System. The location and magnitude of error can be extracted directly from a minimum size lookup table a single error correction and detection using redundant residue number system. [12] Pham, D. M., Premkumar, A. B., & Madhukumar, A. S also design a novel number theoretic transform called Inverse Gray Robust Symmetrical Number System (IGRSNS) for error control coding,. IGRSNS is obtained by modifying Robust Symmetrical Number System (RSNS) that was proposed earlier, using Inverse Gray code property. Due to ambiguities present in each residue, RSNS has a short dynamic range (DR) compared to that in other number systems. The short DR of RSNS enables it to be effectively used for error detection without the addition of any redundant modulus as in Redundant Residue Number System. Although RSNS has a large redundant range, its detection ability is not optimal due to the Gray code property associated with it. In an attempt to overcome this limitation, we have proposed Inverse Gray coding to be combined with RSNS in increasing its effectiveness in error detection, and the algorithm performs well under all cases of single bit errors.

positional residue number system. Originality. The work offered the new effective approaches to solve the non- modular operations of the non-positional residue number system. It seems appropriate to consider these approaches as research areas to enhance the effectiveness of the modular calculation. Practical value. The above solutions have high performance and can be effective in developing modular computing structures.

10. Phatak, D.S.: RNS-ARDSP: A novel, fast residue number system using approximate rational domain scaled precomputations, Part I RP-PR: Reduced precision partial reconstruction and its applica- tion to fast RNS base extensions and/or base-changes. Tech. Rep. TR-CS-10-01, University of Maryland, Baltimore County, CSEE Dept. (2010). UMBC Technical Report TR-CS-10-01. Revised: November, 2013

If a residue number system is designed not only for the representation of data, but also for the protection of data, usually we design the RNS using so-called redundant moduli, in order [r]

the independent residues. Furthermore, the lack of ordered sig- nificance of the residue digits implies that as long as a suffi- ciently high number of residues is available, in order to unam- biguously represent the results of the computations, any erro- neous residue digit can be discarded without affecting the result. Error detection and correction algorithms based on the RNS have been proposed by Szabo et al. [41], as well as by Watson and Hastings [42], which exploited the properties of the redun- dant residue number system (RRNS). More recently, a com- putationally efficient procedure was described in [48] for cor- recting a single error. In [49], the procedure was extended to cor- recting double errors as well as simultaneously correcting single and detecting multiple errors. Efficient soft-decision based mul- tiple error correcting algorithms were suggested in [50]. Fur- thermore, an RNS-based -ary modulation scheme has been proposed and analyzed in [51], while an RRNS-based CDMA system was the topic of [52].

The rest of the paper is structured as follows. Section 2 provides a brief background on residue number system and fault tolerance. In Section 3, the hardware realization of the proposed system was discussed, and the corresponding algorithm is presented in the same section. Section 4 describes the performance evaluation of the proposed converter and evaluates and compares its performance. The paper is concluded in Section 5.

The system Bit Error Rate (BER) and Peak-to-Average Power Ratio (PAPR) were measured through a MATLAB programs for different simulated channel conditions, including the effect of signal amplitude reduction and multipath delay spreading. The simulation results had shown that RRNS coding scheme provides an enhancement BER performance and reduced PAPR in comparison to conventional error detection and correction schemes through using the distinct features of Residue Number System (RNS).

The peak-to-average power (PAPR) is one of the main challenges in multicarrier transmissions. Aiming at reducing the PAPR, we propose a residue number system (RNS)-based OFDM parallel transmission scheme. The key idea of the proposed scheme is to utilize the parallel property of RNS to convert the input signals into the parallel smaller residue signals while utilizing the characteristic of RNS modular operation to effectively limit the output in each residue subchannel after inverse fast Fourier transform, which is smaller than the corresponding modulus. The main contribution of the proposed scheme is to reduce the dynamic range of the transmitted signal without nonlinear distortion so as to reduce the PAPR during the transmission. A generalized performance of the proposed scheme is analyzed in this paper, including the PAPR reduction, the complexity, the transmission bandwidth, etc. Also, an approximate formula to calculate the transmission bandwidth of the proposed scheme is derived, which simplifies design procedure in practice and implies that a minor increase of the dynamic range of RNS will bring comparative improvement of the transmission bandwidth consumption. Theoretical analysis and simulation results demonstrate that the proposed scheme has the

Using discrete wavelet transform (DWT) in high-speed signal processing applications imposes a high degree of caution to hardware resource availability, latency and power consumption. In this paper, we investigated the design and implementation aspects of a multiplier-free two-level DWT by using residue number system (RNS). The proposed two-level takes the advantage of performing the multiplication operations using only the memory without involving special multiplier units, which preserves valuable resources for other critical tasks within the FPGA. The design was implemented and synthesized in ZYNQ ZC706 development kit, taking advantage of embedded block RAMs (BRAMs). The results of the overall experimentations showed that there is a considerable improve in the proposed two-level DWT design with regard to latency and peak signal-to-noise ratio (PSNR) precision value in the final output.

The Residue Number System plays a significant role in the battery based and portable devices because of its low power features and its competitive delay. The Residue number system reverse converter is designed with parallel prefix addition by using new components methodology for higher speed operation[1].The RNS consists of two main components forward and the reverse converter that are integrated with the existing digital system. The forward converter performs the operation of converting the binary number to the modulo number whereas the reverse converter performs the operation of reverse converting the modulo number to the binary number which is the hard and time consuming

ABSTRACT: The use of floating point unit has lot of application in real time embedded systems. Algorithms like fast fourier transform (FFT) from the digital signal processing (DSP) domain often make extensive use of floating point arithmetic. This paper presents the design and implementation of a single precision floating point processor using residue number system (RNS) in FPGA. This processor uses Microprocessor without Interlocked Pipeline Stages (MIPS) instruction set architecture. It is capable of performing both floating point as well as integer operations . The design is done in a way to optimize the performance of the processor using the attractive properties of residue number system such as parallelism and carry free computation. The design is coded in Verilog hardware description language and synthesized with the help of Xilinx ISE tool.

In this paper, we will merge between the usages of DNA sequences and Residue number system in encryption systems. The message which is coded will be secretly impeded inside the DNA sequence. This merge will be leaded to perform multilayer encryption with different keys - that can be used as a hash function - versatile alternatively to increase the security and more flexibility, with less complexity. As the security is one of the most important issues in communication systems, the evolvement of cryptography and cryptographic analysis are considered as the fields of ongoing research. This field is becoming very promising. Thus, a straight forward algorithm that achieves efficiency as multi-layer encryption techniques are implemented.

The objective of this paper is to present the design of a Quinary to Residue Number System (RNS) converter over the Quinary moduli set {23, 24, 25} by using Multi levels of MVL to RNS converters. This method will lead to minimize the number of used logic elements (gates, adders,..) hence reducing the propagation delay, decreasing the chip density and complexity comparing to other methods those are used in binary to RNS conversion.

In Part I of this paper, we focus our attention on the system’s description and on the associated background of the RNS arith- metic, as well as on the performance evaluation of the residue number system arithmetic, using both nonredundant and redun- dant moduli based orthogonal signaling schemes, over an additive white Gaussian noise (AWGN) channel. Redundant RNS codes are introduced in order to protect the transmitted information. The detection techniques used in this novel system are different from conventional detectors. Specifically, a novel decision algorithm, referred to as a ratio statistic test, is designed, which implies dropping some of the lowest reliability demodulation outputs before the residue digits are transformed back to binary symbols. This improves the system’s performance. This dropping technique is different from the conventional “errors and erasures” decoding, where the erased symbols (or bits) should be computed and filled during decoding. We argue that the demodulated/decoded infor- mation can be obtained by decoding the retained or undiscarded symbols upon exploiting the properties of the RNS arithmetic. Our numerical results show that the proposed scheme constitutes a high-efficiency parallel transmission method for high-bit-rate communication, achieving a coding gain of 2 dB at a bit error rate of 10 6 over AWGN channels.

VLSI (Very Large Scale integration) architecture for FIR filters which aims at reducing the power consumption, increasing the speed and also to reduce the hardware complexity using Residue Number System (RNS). This enables simultaneous parallel processing on all the digits resulting in high speed addition and multiplication in RNS domain. It uses modulo adders and modulo multipliers to obtain high speed performance.

Residue number system (RNS) is gaining enhancing popularity in the VLSI implementation of application- specific digital signal processors (DSPs). This is in part due to its ability to accelerate and to decrease the power consumptions of crucial and frequently used data path operations by subword-level parallelism and modularity, and in part due to the ease of realizing modulo operations using the moduli of the forms 2 n and 2 n ±1. Modular 2 n ±1. arithmetic properties have been exploited with arithmetic structures, such as diminished-1, sparse carry chain, Kogge–Stone adder, and so on, to decrease the implementation complexity of modulo addition, subtrac- tion, and multiplication for these special moduli to an extent that is comparable with their two’s complement number system counterparts. These improvements have given rise to the extensive use and continual successes in developing the balanced three moduli set {2 n − 1, 2 n , 2 n + 1} for the implementation of many new and exist- ing DSP algorithms, including fast Fourier transform, discrete wavelet transform, finite and infinite impulse response filters, and digital image processing. In fact, the difficulties associated with the implementation of nonmodular operations, such as scaling and reverse conversion from residue-to-binary representation, have largely been resolved for this three moduli set.

I N RECENT years, the so-called residue number system (RNS) arithmetic has attracted considerable attention for supporting fast arithmetic operations [1]–[8]. The arithmetic advantages accrue from the property that the RNS has the ability to add, subtract, or multiply in parallel, regardless of the size of the numbers involved, without having to generate intermediate carry forward digits, which would slow down the execution of operations [1]. By adding a number of redundant moduli, the so-called redundant RNS (RRNS) is obtained. RRNSs have been studied extensively for the fault-tolerant execution of arithmetic operations in digital filters and in general purpose computers [1]–[8]. A range of further novel applications in the context of RRNS-aided orthogonal frequency-division multi- plexing (OFDM) and code-division multiple-access (CDMA) systems was proposed in [9] and [11]–[14].

Residue Number System (RNS) is an integer number system with the competency to support parallel, carry-free addition, borrow-free subtraction and single step multiplication without unfinished product. These features enable RNS utilization in Digital Signal Processing (DSP) applications such as convolution, fast Fourier transform, digital filtering and image processing [4], [5]. For triumphant application of RNS, data conversion must be very fast so that the conversion outlay doesn’t nullify the RNS advantages [4].