[PDF] Top 20 WRL TN 13 pdf

... 2 large sprigs of dill 4 pounds of small unwaxed cucumbers 3 peeled garlic cloves optional 1 dried chili pepper 1 teaspoon mixed pickling spice 1/8 teaspoon alum 7 cups water 1/3 cup kos[r] ... See full document

... The previous sections have only discussed instruction caches. A natural question is whether the same techniques can be applied to data caches as well. Figure 13 shows the result of using the single bit dynamic ... See full document

... In the sleep-mode experiments, the processor must exit sleep mode, re-initialize part of the hardware, send the string of characters, and re-enter sleep mode. According to the StrongARM SA-1100 manual [Int99] it takes ... See full document

... To perform our evaluation, we collected information from 43 C and FORTRAN programs. We instrumented the programs from the SPEC92 benchmark suite and other programs, including many from the Perfect Club [2] suite and a ... See full document

... Line 5 of the instrumentation file declares the Reference analysis procedure. The type VALUE indicates that the argument does not live in a processor register, but must be computed by ATOM prior to passing the value to ... See full document

... Under the beta model we see roughly the same behavior, though it is not as pronounced. Now the mean payoff of the biggest predictor over the 1-kilobit predictor is about 14%. When we eliminate first register renaming and ... See full document

... One combination of branch predictors that is useful is bimodal/gshare. In this com- bination, global information can be used if it is worthwhile, otherwise the usual branch direction as predicted by the bimodal scheme ... See full document

... Figure 13 compares boiling curves of water and 2-propanol mixtures. The system temperature was maintained at 38.9°C. In each figure, the binary mixture boiling curve is plotted against the pure fluids at the same ... See full document

... and Mom during a cell write operation. For this example Mom is 41 times faster than SPICE. An increasing number of circuit designs utilize both bipolar and MOS transistors on the same chip. Unfortunately neither Rsim nor ... See full document

... caches. For caches of this size access times of 16 to 30ns are likely. This yields an access time for the cache of 4 to 30 instruction times. The relative speed of the processor as compared to the access time of the ... See full document

... Our research is directed towards mainstream high-performance computer systems. Our prototypes are intended to foreshadow the future computing environments used by many Digital customers. The long-term goal of WRL ... See full document

... The Western Research Laboratory (WRL) is a computer systems research group that was founded by Digital Equipment Corporation in 1982. Our focus is computer science research relevant to the design and application ... See full document

... A new version of the WRL tracing facilities collected traces on DECstation 5000’s running ULTRIX [4, 5]. Its kernel-based approach traces all processes. The modified system logs system call information in a ... See full document

... We want our IIS systems to handle as high a request rate as possible, but when that rate is exceeded, we do not want them to suffer from congestive collapse or ‘‘livelock.’’ A livelocked[r] ... See full document

... For unaligned source and destination pointers, the server reads each source word once, and writes each destination word once, which requires the processor to rotate and merge words. On the R2000, this operation takes ... See full document

... List of Figures Figure 1: Effect of increasing line size on capacity and compulsory misses Figure 2: Effect of increasing line size on overall miss rate Figure 3: Effect of increasing da[r] ... See full document

... The author is also indebted to the Itsy team at the Western Research Laboratory (WRL) and System Research Center (SRC): Joel Bartlett, Lawrence Brakmo, David Chaiken, Je Dean, Puneet Kumar, Bob Mayo, Sharon Perl, ... See full document

... We do work in the design, fabrication and packaging of hardware; language processing and scaling issues in system software design; and the exploration of new applications areas that are opening up with the advent of ... See full document

... at WRL ranges from Web search engines to tools to optimize binary codes, from hard- ware and software mechanisms to support scalable shared memory paradigms to graphics VLSI ...of WRL tradition, we test our ... See full document

... at WRL includes Internet protocol design and implementation, tools for binary optimization, hardware and software mechanisms to support scalable shared memory, graphics VLSI ICs, handheld computing, and ...at ... See full document