T here are 21 branch instructions defined for the HC11. T hree of these instructions, BRCLR, BRSET and BSR, have special applications. T heir function will not be presented in this section. BRCLR and BRSET are described in chapter 9, and BSR is described in chapter 6. T he function of the remaining 18 branch instructions will be the focus of this section.
Each branch instruction performs a test to determine if the branch will be taken. As each test has a complementary form, the instructions are paired. For example, branch if equal to zero (BEQ) is complementary to branch if not equal to zero (BNE). BEQ will cause a branch to occur if the Z flag of the CCR is set, which indicates that the result of a prior instruction was zero. BNE will cause a branch to occur if the Z flag of the CCR is cleared, which indicates that the result of a prior instruction was not zero. The branch instructions are categorized into functional groups for presentation in this text. These functional groups are unconditional, conditional-simple, conditional-
1. What kind of address is used by all branch instructions?
2. If the address of a BRA instruction is $0023 and the Offset = $62, what is the destination address?
3. If the address of a BRA instruction is $B61D and the Offset = $9A, what is the destination address?
4. Calculate the relative address (rr) for each of the following branch instructions.
0193 20 ?? BRA END
⋅ ⋅ ⋅
01DD E6 00 END LDAB 0,X
5. Calculate the relative address (rr) for each of the following branch instructions.
E25A 97 25 MSG1 STAA $25
⋅ ⋅ ⋅
E273 20 ?? BRA MSG1
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unsigned and conditional-signed. Each functional group is described in subsequent sections. Figure 4.6 summarizes the 18 branch instructions. All branch instructions use the relative addressing mode and have no affect on the CCR.
Unconditional Branching
There are two unconditional branch instructions: BRA and BRN. The BRA instruction always passes the branch test and will always branch, as the mnemonic implies (BRA = Branch Always). The BRN instruction never passes the branch test and will never branch, as the mnemonic implies (BRN = Branch Never). The BRN instruction is very useful during troubleshooting to replace another branch instruction as well as in timing loops to cause a time delay.
Conditional Branching
The branch tests are simple if they consist of testing the state of a single bit in the CCR. The branch tests are “unsigned” because they perform a branch test from an unsigned perspective. The unsigned perspective ignores the sign bit and views all eight (or sixteen) data bits as magnitude. Each of these tests is concerned about the relationship of two unsigned data words. The branch tests are “signed” because they perform a branch test from a signed perspective. The signed perspective views the MSB as a sign bit and the remaining bits as a 2’s complement magnitude. Each of these tests is
Mnemonic Description
Boolean Conditional
Test
Complement
Form Functional Group BRA Branch always Always passes BRN Unconditional BRN Branch never Never passes BRA Unconditional BCC Branch if carry cleared (see BHS) ? C = 0 BCS Conditional-simple BCS Branch if carry set (see BLO) ? C = 1 BCC Conditional-simple BEQ Branch if equal to zero ? Z = 1 BNE Conditional-simple BMIBranch if minus (negative) ? N = 1 BPL Conditional-simple BNE Branch if not equal to zero ? Z = 0 BEQ Conditional-simple BPL Branch if plus (positive) ? N = 0 BMIConditional-simple BVC Branch if overflow cleared ? V = 0 BVS Conditional-simple BVS Branch if overflow is set ? V = 1 BVC Conditional-simple BHIBranch if higher ? C + Z = 0 BLS Conditional-unsigned BHS Branch if higher or same (see BCC) ? C = 0 BLO Conditional-unsigned BLO Branch if lower (see BCS) ? C = 1 BHS Conditional-unsigned BLS Branch if lower or same ? C + Z = 1 BHIConditional-unsigned BGE Branch if greater than or equal ? N ⊕ V = 0 BLT Conditional-signed BGT Branch if greater than ? Z+(N⊕V) = 0 BLE Conditional-signed BLE Branch if less than or equal ? Z+(N⊕V) = 1 BGT Conditional-signed BLT Branch if less than ? N ⊕ V = 1 BGE Conditional-signed
Figure 4.6 Summary of Branch Instructions
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concerned about the relationship of two signed data words. Although BEQ and BNE are conditional-simple, they are used for equality tests in all groups because equal is equal regardless of the sign of the data.
Each of the conditional branch instructions requires that a branch test be performed before the address of the next instruction is calculated. The branch test consists of evaluating a Boolean expression to determine if the condition has been met. For example, if the program is concerned about overflow conditions, it might perform a BVS instruction. The BVS instruction tests to see if the V flag in the CCR is set. The test is shown as ?V = 1, which is read as “does V = 1?” If the V flag is set, the BVS will cause the displacement to be added to the value in the program counter to calculate the address of the next instruction to execute.
NOTE: The branch test is a Boolean expression that must be evaluated before the branch can take place. If the expression evaluates to a true state, the branch test passes and the branch takes place. If the expression evaluates to a false state, the branch test fails and the program falls through to the next instruction.
Some of the conditional-unsigned branches and all of the conditional-signed branches evaluate a Boolean expression for the branch test. Rather than testing for the state of a single bit, each of these branch tests evaluates the status of two or three bits. For example, the branch if less than (BLT) instruction evaluates the Boolean expression, “? N ⊕ V = 1”, which is read “Is (N XOR V) equal to 1?” The HC11 performs this test with logic gates, as shown in Figure 4.7. The condition is true only when N and V are opposites.
To emphasize the concept of evaluating the Boolean expression, one more example will presented. Consider the branch if greater than (BGT) instruction. It evaluates the Boolean expression, “? Z + (N ⊕ V) = 0”, which is read “Is (Z OR (N XOR V)) equal to 0?” The HC11 performs this test with logic gates, as shown in Figure 4.8. The condition is true only when Z is zero and N and V are equal.
Example 4.3
Problem: Calculate the destination address for each of the following conditional branch instructions if the CCR register contains $DA before the branch is executed.
N CCR N V XOR Test 0 0 0 1 0 1 0 1 1 1 1 0 fail
N + V = 1 only when N and V are opposites, as shown in truth table. pass fail Test 1? I Z V C H X S
Figure 4.7 BLT Branch Test (? N ⊕ V = 1)
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Address Machine Code Source Code a. 01D9 2B 0C BMI PAST b. 0112 25 53 BCS LOOP c. B6C3 23 8B BLS AGAIN d. E0F4 2E F2 BGT AGAIN
Solution: In each case, the processor must determine if the branch test passes or fails. In addition, the contents of the PC must be determined. If the test fails, DA = PC. If the test passes, then the sign-extended relative address must be added to the PC to calculate the destination address (Equation 4.1). Since each of these instructions occupies two bytes of memory, the address of the next instruction (PC) will be two greater than the address of the branch instruction.
CCR = $DA, thus N = 1, Z = 0, V = 1, C = 0.
a. BMI test checks if N = 1. Since N = 1, the test passes and DA = PC + rr.
PC = $01D9 + 2 → $01DB
rr = $0C, sign extend → $000C
DA = PC + rr → $01E7
b. BCS test checks if C = 1. Since C = 0, the test fails and DA = PC. DA = PC = $0112 + 2 → $0114
c. BLS test checks if Z or (N XOR V) = 0. Since Z = 0 and (N XOR V) = 0, then the test passes and DA = PC + rr.
DA = PC = $B6C3 + 2 → $B6C5
d. BGT test checks if N = 1. Since N = 1, the test passes and DA = PC + rr.
PC = $E0F4 + 2 → $E0F6
rr = $F2, sign extend → $FFF2
DA = PC + rr → $E0E8
Many instructions update the status flags with the information necessary to complete the branch test. For example, when an LDAA instruction is executed, the N and Z flags
N Z N + V 0 0 Z + (N + V) 0 1 1 1 0 1 1 0 1 1 1 N 0 1 1 0 1 0 V 0 0 0 0 1 1 0 0 1 0 0 0 1 1 0 1 1 1 1 1 1
Z + (N + V) = 0 only when both Z and (N + V) are equal to zero, as shown in truth table.
Test 0? I Z V C H X S
Figure 4.8 BGT Branch Test (?Z + (N ⊕ V) = 0) 103
are updated with the state of the data that was loaded. The C flag is also cleared by an LDAA instruction. A conditional branch instruction can immediately follow and perform branch tests relevant to the status recorded during the LDAA instruction.
Example 4.4
Problem: Calculate the destination address for the following conditional branch instruction.
Address Machine Code Source Code
01D3 C6 84 LDAB #$84
01D5 2B 03 BMI PAST
Solution: The processor must determine if the branch test passes or fails. In addition, the contents of the PC must be determined. If the test fails, DA = PC. If the test passes, then the sign-extended relative address must be added to the PC to calculate the destination address (Equation 4.1). Since the branch instruction occupies two bytes of memory, the address of the next instruction (PC) will be two greater than the address of the branch instruction.
Since the data loaded by the LDAB is negative, then the N flag in the CCR will be set. Because BMI test checks if N = 1, then the test passes and DA = PC + rr.
PC = $01D5 + 2 → $01D7
rr = $03, sign extend → +$0003
DA = PC + rr → $01DA