Each member of the HC11 microcontroller family has built-in memory. There are slight differences on each version of the chip, as shown in Figure 8.5. Each version contains RAM and at least one type of ROM (ROM, EPROM or EEPROM).
Each of these memory components is mapped into the address space. The memory
map is a layout of where each memory block resides within the entire address space. 177
$000 $00F $00E $00D $00C $00B $00A $009 $008 $007 $006 $005 $004 $003 $002 $001 $010 $01F $01E $01D $01C $01B $01A $019 $018 $017 $016 $015 $014 $013 $012 $011 $030 $03F $03E $03D $03C $03B $03A $039 $038 $037 $036 $035 $034 $033 $032 $031 $020 $02F $02E $02D $02C $02B $02A $029 $028 $027 $026 $025 $024 $023 $022 $021 Data Bus
Figure 8.4 Addressing of a Memory Module
1. What is an address?
2. Can an address contain more than one part? If so, give an example.
3. Why is the layout of a self-storage facility similar to the layout of a computer memory?
This memory map is unique for each version of the HC11. On the HC11, user programs have no concern for the type of memory being accessed during read operations because all the memory types allow read operations. The RAM, EEPROM, ROM and external memory are read in the same manner. Each of these memory devices responds to a read operation within the constraints of the processor machine cycles. In other words, the memory during a read operation is at least as fast as the processor can generate read operations.
The ROM is of course “read only,” so write operations make no change to the ROM memory locations. The EEPROM is also “read only,” but data can be changed by a special programming operation. The RAM is general-purpose read-write memory.
T he function of the EEPROM programming operation is explained in section 8.4.
Self-Test Questions 8.2
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Part Number RAM EEPROM ROM EPROM Comments
MC68HC11A8 256 512 8K —- Entire HC11 family is built around this version of
the device
MC68HC11A1 256 512 —- —- ‘A8 with ROM disabled
MC68HC11A0 256 —- —- —- ‘A8 with ROM & EEPROM disabled
MC68HC811A8 256 8K + 512 —- —- ‘A8 with EEPROM instead of ROM
MC68HC11E9 512 512 12K —- Enhanced A8—Four IC functions, more RAM
and ROM (used on the EVBU)
MC68HC11E1 512 512 —- —- ‘E9 with ROM disabled
MC68HC11E0 512 —- —- —- ‘E9 with ROM & EEPROM disabled
MC68HC811E2 256 2K —- —- ‘E9 with more EEPROM, no ROM
MC68HC711E9 512 512 —- 12K ‘E9 with EPROM instead of ROM
MC68HC11D3 192 —- 4K —- Budget A8—40-pin package, reduced
functionality
MC68HC711D3 192 —- —- 4K ‘D3 with EPROM instead of ROM
MC68HC11F1 1024 512 —- —- Enhanced A8—non-multiplexed expanded
memory bus independent of PORTB and PORTC, 68-pin package
MC68HC11K4 768 640 24K —- Enhanced A8—larger address bus, PWM, CS,
more memory, 84-pin package
MC68HC711K4 768 640 —- 24K ‘K4 with EPROM instead of ROM
MC68HC11L6 512 512 16K —- Enhanced E9—more I/O, more ROM, 64- and 68-
pin packages
MC68HC711L6 512 512 —- 16K ‘L6 with EPROM instead of ROM
Figure 8.5 HC11 Memory Configurations (adapted with permission from Motorola)
1. Do all versions of the HC11 microcontroller contain on-chip memory? 2. How much RAM is contained on the K4 version of the HC11?
3. What is the difference between the HC11E9 version and the HC711E9 version?
8.3 R AM
There are two primary types of RAM: static and dynamic. All static memory devices use a latch as the storage cell. Each bit of binary data is stored in a single latch. The term
static refers to the fact that the state of a latch remains static or unchanged so long as power is applied or the new data is latched into the device. In contrast, dynamic RAM (DRAM) devices use a capacitor to store the data bits. Unlike a static device, a capacitor is constantly discharging or the voltage level is dynamic. All DRAM devices require refresh circuitry to keep the charge levels on the capacitors at the proper level to retain the 1’s and 0’s stored in them.
Every version of the HC11 contains SRAM. The HC11E9 contains 512 bytes that are fully functional read-write memory. The RAM is typically used for the storage of variables and data during program execution, yet it can also contain executable programs. In a microcontroller environment, executable programs are usually pro- grammed into a nonvolatile memory (ROM or EEPROM) so that the programs are not inadvertently lost from power loss or erasure.
Location of RAM in HC11 Memory Map
The HC11E9 RAM is located by default at $0000–$01FF in the memory map. The user can move the location of the RAM in the memory map by changing the RAM map position control bits in the INIT register, as shown in Figure 8.6. These four bits specify the most-significant hex digit of the 16-bit RAM address in the memory map. The location can be changed to the start of any 4K memory block, as shown in Figure 8.7. 4K is the maximum number of memory locations that can be addressed with the remaining 12 bits of the 16-bit address bits (212 = 4K).
NOTE: The INIT register is one of four protected control registers (BPROT, INIT, OPTION and TMSK2). In order to protect the sensitivity of the bits in the INIT register, write operations are protected in normal processor modes except under special circumstances. The INIT register can only be written once and that write must occur in the first 64 machine cycles after reset.
The ability to relocate the RAM in the address space allows the user to have greater flexibility with on-chip and off-chip resources. Address decoding circuitry is simplified if the memory device can be located in the zero page of the memory map. If the on-chip RAM were remapped to a higher memory area, the 4K zero page of the memory would be available for external connection.
179
INIT b7 b6 b5 b4 b3 b2 b1 b0
$103D RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0
RESET 0 0 0 0 0 0 0 1
Figure 8.6 RAM Map Position
Overlapping Memory Devices
The HC11 also allows the on-chip RAM, register block and ROM to be mapped to the same address space. They can also be mapped to the same space as an external memory device. The HC11 has internal address decode circuitry that automatically protects against memory access conflicts when the memory address space overlaps. When an internal device is read, the external bus is ignored, even if the external device drives the bus. Conflicts between on-chip resources are resolved with priority circuitry. The register block always has the highest priority, then the RAM, followed by the ROM. On the HC11E9 the register block and RAM could be remapped to the same space, starting at $D000, as shown in Figure 8.8. In this case, the register block would respond to any memory accesses from $D000 to $D03F. The RAM and ROM would be disabled for this range. The RAM would respond to memory accesses from $D040 to $D1FF. The ROM would be disabled for this range. The ROM would then be active for the remainder of the 12K space from $D200 to $FFFF.
RAM on the EVBU
The BUFFALO monitor program on the EVBU uses a large portion of the RAM for the temporary storage of variables, data, the user stack and the interrupt vector jump table. Sometimes this area of RAM is called the scratch pad because of the way the BUFFALO monitor program uses it. BUFFALO reads and writes data to and from this area in a way similar to the way people jot notes on a scrap of paper. Figure 8.9 shows the layout of the scratch pad RAM area.
180
RAM[3:0] (Binary)
RAM[3:0]
(Hex) Address Range
0000 $0 $0000 - $01FF 0001 $1 $1000 - $11FF 0010 $2 $2000 - $21FF 0011 $3 $3000 - $31FF 0100 $4 $4000 - $41FF 0101 $5 $5000 - $51FF 0110 $6 $6000 - $61FF 0111 $7 $7000 - $71FF 1000 $8 $8000 - $81FF 1001 $9 $9000 - $91FF 1010 $A $A000 - $A1FF 1011 $B $B000 - $B1FF 1100 $C $C000 - $C1FF 1101 $D $D000 - $D1FF 1110 $E $E000 - $E1FF 1111 $F $F000 - $F1FF
Figure 8.7 RAM Mapping
NOTE: The BUFFALO Monitor program requires that the RAM be mapped in the default range of $0000–$01FF.