Available RAM Available ROM $D000 $D03F $D040 $D1FF $D200 $FFFF ROM Mapped $D000–$FFFF RAM Mapped $D000–$D1FF
Figure 8.8 Overlapping Memory Map
$0000 $002C $002D $0041 $0042 RAM Memory MAP
$005F $0060 $00C3 $00C4 $00FF $0100 $01FF
Available for user programs Default user stack BUFFALO monitor stack
BUFFALO variable space
Interrupt Vector Jump Table
Available for user programs
1. What is the default memory location of the RAM on the EVBU? Can this location be changed?
2. How is the RAM used by the BUFFALO monitor program?
Figure 8.9 RAM Contents on EVBU 181
8.4 EEPROM
The HC11 supports on-chip EEPROM. The HC11E9 contains 512 bytes of EEPROM. The EEPROM is typically used to contain user executable programs, yet can also be used to store any data that requires more security from loss. The EEPROM on the HC11E9 is mapped to $B600–$B7FF. Unlike the RAM and the register block, the EEPROM cannot be remapped to another page of the unused memory. The on-chip EEPROM can be disabled via the EEON control bit of the CONFIG register. When the EEPROM is disabled, it is effectively removed from the memory map. Figure 8.10 illustrates where the EEON bit is located in the CONFIG register. When EEON = 1, the on-chip EEPROM is enabled. When EEON = 0, the on-chip EEPROM is disabled. The state of the EEON bit after reset is undefined. The E9 version of the chip used on the EVBU is shipped from Motorola with the CONFIG register set to $0F.
NOTE: As the CONFIG register is implemented in EEPROM, its contents remain unchanged after power loss; however, it is a separate 8-bit EEPROM. Other than the EEON bit, the CONFIG register has no connection to the EEPROM memory block.
Operation of the EEPROM
EEPROM by nature acts like a ROM, thus it is nonvolatile. During read operations, it acts like any memory location; however, the EEPROM requires special handling when data is being written to an EEPROM memory location. Write operations to an EEPROM location can only be performed by programming a location in the EEPROM.
Most EEPROM devices require special programming voltages and often require special hardware fixtures designed specifically for write operations. The EEPROM on the HC11 is designed so that none of the special hardware is needed. It can be reprogrammed via software control without the use of external circuitry or a special power supply. The EEPROM on the HC11 is logically arranged in 32 rows of 16 bytes each. The first row occupies the locations $B600–$B60F, the second row occupies $B610–$B61F, and so on. Before a location in the EEPROM is written (programmed), it should be erased to assure that all bits in that location are high. The process of writing data into a location of the EEPROM removes fuse connections from the fuse map for all zeros in the data. Ones in the data cause the fuses to be left in place. Thus, all locations need to be connected prior to the write operation.
The EEPROM Programming register (PPROG) contains seven bits that control the operation of the EEPROM on the HC11. They layout of this register is shown in Figure
CONFIG b7 b6 b5 b4 b3 b2 b1 b0
$103F − − − − NOSEC NOCOP ROMON EEON
RESET 0 0 0 0 U U 1 U
Figure 8.10 EEON Control Bit in the CONFIG Register
182
8.11. The ODD and EVEN control bits allow all locations in either the odd or the even half of the EEPROM array to be programmed with the same data simultaneously. They are used only during factory testing of the EEPROM. Bit 5 is unused and is always read as a zero.
EEPROM locations can be erased one at a time, in rows of 16 locations or all 512 bytes at once. The BYTE and ROW bits are used to determine the type of erase to perform when the ERASE bit is set, as shown in Figure 8.12. When ERASE = 1, the EEPROM can be erased. The BYTE controls single-byte erasures, and the ROW bit determines whether a ROW or the entire EEPROM will be erased. When ERASE = 0, the EEPROM is configured for normal read or programming mode.
The EEPROM Latch control bit (EELAT) controls the operations of the EEPROM. When EELAT = 0, the EEPROM is configured for normal reads. When EELAT = 1, the EEPROM is configured for programming or erasing. When EELAT = 1, the EEPROM is effectively removed from the memory map; thus it is not accessible during the relatively long time it requires to complete the erase or write operations. The relationship of the ERASE and EELAT bits is shown in Figure 8.13.
The LSB of the PPROG register is the EEPROM Programming Voltage Enable (EPGM or EEPGM in some literature). It is used to switch on the programming voltage to the EEPROM array, which is necessary for the erase and write operations. The HC11 uses an internal charge pump to build up the programming voltage so that an external
PPROG b7 b6 b5 b4 b3 b2 b1 b0
$103B ODD EVEN − BYTE ROW ERASE EELAT EPGM
RESET 0 0 0 0 0 0 0 0
Figure 8.11 PPROG Register
BYTE ROW
Erase Action when ERASE = 1
0 0 Bulk Erase (Entire array) 0 1Row Erase (16 bytes) 1X Byte Erase
Figure 8.12 EEPROM Erase Options
183 ERASE EELAT Function when EPGM = 1 0 0 EEPROM Read 0 1EEPROM Write 10 Undefined 11EEPROM Erase
Figure 8.13 ERASE and EELAT Functions
programming voltage is not required. This charge pump is activated when EELAT = 1. The charge pump must be activated before the HC11 will allow the programming voltage to be applied to the EEPROM array. The internal circuitry prevents the EPGM bit from being set unless the EELAT bit was previously set.
NOTE: The EELAT bit must be set in an operation prior to the operation that sets the EPGM bit. This is required to allow sufficient time for the internal charge pump to raise the programming voltage to the proper level. If the user attempts to set the EELAT and EPGM bits in the same operation (when they were both previously cleared), neither bit will be set.
Erasing the EEPROM
The EEPROM must be erased to assure all bits are 1’s prior to a write operation. A write operation can only clear 1’s; thus, bits that are already zero in an EEPROM location cannot be set to one with the write operation. Although there are three options available to erase EEPROM locations, the same process must be followed. Figure 8.14 lists the steps necessary to successfully erase EEPROM locations.
The code segments shown in Figure 8.15 illustrate how the procedure from Figure 8.14 can be implemented to erase the entire EEPROM, a row of 16 bytes in the EEPROM or a single location within the EEPROM. The three examples illustrate that there are only slight differences in the code, but significant differences in the results.
NOTE: The CONFIG register is implemented in EEPROM; however, it has no relationship to the EEPROM memory block. Therefore, none of the EEPROM code segments affects the contents of the CONFIG register.
Writing to the EEPROM
The EEPROM write operation is referred to as EEPROM programming. It follows a process similar to the steps of an erase operation, which is outlined in Figure 8.16.
Step Description
1Set the EELAT and ERASE bits of the PPROG register to prepare the EEPROM for erasure and select the desired erase operation (BYTE, ROW) as described in Figure 8.12.
2 Write any data to the EEPROM. The write operation is used only to indicate to the EEPROM control hardware which locations are to be erased; the value of the data is irrelevant. If the entire EEPROM is selected, any location within the EEPROM can be selected. If a row is being erased, then the location must be within the target row. A single location must addressed for it to be erased.
3 Set the EPGM bit in the PPROG register to start the erasure.
4 Wait 10 ms for the erasure to complete. (In some cases, the required delay may be longer than 10 ms.)
5 Clear all the bits in the PPROG register to deactivate the erase function.
Figure 8.14 Steps Necessary to Erase EEPROM Locations
184
During a write to the EEPROM, the ROW and BYTE bits of the PPROG register are not used. Data must be written to the EEPROM one byte at a time. As the erase operation, the write operation requires a 10 ms delay to allow the programming to complete. The code segment shown in Figure 8.17 illustrates one method that can be used to write a single byte of data to the EEPROM.
BULKE LDAB #%00000110 ;ERASE=1, EELAT=1 STAB $103B ;Activate BULK erase
STAB EEADD ;Write any data to any EEPROM address to ; initialize erase operation
LDAB #%0000111 ;ERASE=1, EELAT=1, EPGM=1 STAB $103B ;turn on programming voltage JSR DLY10MS ;Wait 10 ms
CLR $103B ;ERASE=0, EELAT=0, EPGM=0
ROWE LDAB #%00001110 ;ROW=1, ERASE=1, EELAT=1
STAB $103B ;Activate BULK erase
STAB EEADD ;Write any data to EEPROM address in row ; to initialize erase operation of row LDAB #%00001111 ;ROW=1, ERASE=1, EELAT=1, EPGM=1 STAB $103B ;turn on programming voltage JSR DLY10MS ;Wait 10 ms
CLR $103B ;ROW=0, ERASE=0, EELAT=0, EPGM=0
BYTEE LDAB #%00010110 ;BYTE=1, ERASE=1, EELAT=1 STAB $103B ;Activate BULK erase
STAB EEADD ;Write any data to any EEPROM address to ; initialize erase operation of address LDAB #%00010111 ;BYTE=1, ERASE=1, EELAT=1, EPGM=1 STAB $103B ;turn on programming voltage JSR DLY10MS ;Wait 10 ms
CLR $103B ;BYTE=0, ERASE=0, EELAT=0, EPGM=0
c) Byte Erase b) Row Erase a) Bulk Erase
Figure 8.15 Examples of Code for Erasing the EEPROM
Step Description
1Set the EELAT bit and clear the ERASE bit of the PPROG register to prepare the EEPROM to receive data.
2 Write data to the EEPROM location. The write instruction does not accomplish the physical write but indicates to the EEPROM control hardware which location is targeted to receive the data that is provided.
3 Set the EPGM bit in the PPROG register to start the write.
4 Wait 10 ms for the write to complete. (In some cases, the required delay may be longer than 10 ms.)
5 Clear all the bits in the PPROG register to deactivate the write function.
Figure 8.16 Steps Necessary to Write to an EEPROM Location
WRITEE LDAB #%00000010 ;EELAT=1
STAB $103B ;Activate BULK erase
STAB EEADD ;Write any data to any EEPROM address to ; initialize write operation for that address LDAB #%00000011 ;EELAT=1, EPGM=1
STAB $103B ;turn on programming voltage JSR DLY10MS ;Wait 10 ms
CLR $103B ;BYTE=0, ERASE=0, EELAT=0, EPGM=0
Figure 8.17 Example of Code for Writing a Byte to the EEPROM 185
EEPROM Clock
If the E clock is below 2 MHz, the 10 ms time delay may need to be increased to assure proper operation during EEPROM writes. If a longer delay is not an acceptable option, then the Clock Select (CSEL) bit of the OPTION register may have to be set. Figure 8.18 illustrates the location of the CSEL bit in the OPTION register. When CSEL = 1, the on-chip RC oscillator will drive the programming voltage (VPP) instead of the E
clock. When CSEL = 0, the E clock is used as the main clock for the EEPROM programming system. The CSEL bit is cleared after reset.
NOTE: CSEL is used to determine the charge pump clock source for the A/D conversion hardware as well as the EEPROM programming hardware. Setting CSEL for the EEPROM function automatically reconfigures the A/D function.
EEPROM Security
The HC11 provides a mechanism to protect the contents of the EEPROM from inadver- tent writes or erasure. The Block Protect bits for the EEPROM (BPRT3–BPRT0) are located in the Block Protect register (BPROT), as shown in Figure 8.19. The BPRT3– BPRT0 bits control this EEPROM protection function. When these bits are cleared, programming and erasure of blocks of the EEPROM memory area is allowed. When these bits are set, programming and erasure are inhibited. The bits are set after reset and must be cleared by user software to allow EEPROM programming and erasure.
Each bit controls a block of the EEPROM, as shown in Figure 8.20. Each bit protects a unique block of the EEPROM. The blocks are different sizes, which allows greater
OPTION b7 b6 b5 b4 b3 b2 b1 b0
$1039 ADPU CSEL IREQ DLY CME − CR1 CR0
RESET 0 0 0 1 0 0 0 0
Figure 8.18 Clock Select for EEPROM system.
BPROT b7 b6 b5 b4 b3 b2 b1 b0
$1035 − − − PTCON BPRT3 BPRT2 BPRT1 BPRT0
RESET 0 0 0 1 1 1 1 1
Figure 8.19 EEPROM Block Protect Control Bits
Figure 8.20 EEPROM Protection Blocks
Bit Name Block Size Block Address Range BPRT0 32 $B600 - $B61F BPRT1 64 $B620 - $B65F BPRT2 128 $B660 - $B6DF BPRT3 288 $B6E0 - $B7FF
186
versatility. When a single block is not protected, it is available for normal programming and erasure, even though the remaining blocks are protected.
NOTE: The BPROT register is one of four protected control registers (BPROT, INIT, OPTION and TMSK2). In the normal processor modes the bits in the BPROT register can be cleared only in the first 64 machine cycles after reset. The bits can be set at anytime during program operation. BUFFALO clears the BPROT register immediately following reset.
EEPROM on the EVBU
The BUFFALO monitor program on the EVBU does not use the EEPROM. All 512 bytes are available for user programs and data. Although the BUFFALO monitor program does not use the EEPROM, it provides five subroutines to program or erase the EEPROM. EEWRIT is used to write a byte of data to a particular location in the EEPROM. EEBYTE is used to erase a single location, and EEBULK is used to erase the entire EEPROM. Another routine called WRITE will write data to any memory location, including addresses in the EEPROM; if the EEPROM location is not erased, a byte-erase operation will be performed before the write is completed. The fifth subroutine is a 10 ms delay called DLY10MS.
WRITE, EEWRIT, EEBYTE and EEBULK use the X register to specify the memory location to process. WRITE and EEWRIT use the A register to contain the data that is to be written to the location specified in the X register. The 10 ms delay is automatically called by each of these subroutines, eliminating the need for the user to manage the required 10 ms delay. These subroutines do not affect any other registers.
Refer to Figure 6.16 for a brief explanation of the EEPROM subroutines as well as their location in BUFFALO.
Self-Test Questions 8.4
8.5 R OM
The primary use of the on-chip ROM is storage of user’s application programs. These programs cannot be changed, because they are programmed in the unit during the manufacturing process. Each series of the HC11 family of microcontrollers has a development version that has EPROM or EEPROM in lieu of ROM. This allows the user to develop and modify the programs on a single device. When the programs are debugged, an order can be placed for a high-quantity production version that will contain the user programs in ROM.
1. Describe the various methods available to erase the EEPROM. 2. Briefly, describe the steps required to write to the EEPROM.
3. What can be done to protect the contents of the EEPROM from accidental write or erasure?
187
The on-chip ROM can be disabled by a control bit in the CONFIG register, as shown in Figure 8.21. The ROMON control bit is set after reset enabling the on-chip ROM. When the ROMON bit is cleared, the on-chip ROM is disabled. When the on-chip ROM is disabled, none of the memory space is used for ROM. The user typically disables the on-chip ROM when the user programs are located in an external memory chip. Versions of the HC11 that do not contain ROM, such as the M68HC11E1, still have on-chip ROM, but it is disabled permanently. The ROM is disabled because the ROMON is permanently set to zero in the CONFIG register.
ROM on the EVBU
The BUFFALO monitor program on the EVBU is located in the ROM. It occupies the memory space from $E000 to $FFFF. The first 4K page of ROM from $D000 to $DFFF is unused and unavailable. The Interrupt Vector Table occupies the last 42 bytes of the addressable memory space, $FFD6–$FFFF, located in ROM. The BUFFALO is pro- grammed into the ROM memory during manufacturing; thus it cannot be changed by the user.
See chapter 9 for further information on interrupts and the use of the interrupt vector table.