CMOS power integrated circuits
Reduction of Static Power in CMOS Circuits by Using Biasing and Body Biasing Techniques
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Leakage Power Reduction in CMOS VLSI Circuits
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Capacitance Measurement Methods for Integrated Sensor Applications
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Low Power Ripple Carry Adder Design Using MTCMOS Technique
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Design of Low Power Energy Efficient CMOS Circuits with Adiabatic Logic
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Ultra-Low Power Design of Digital CMOS Logic Circuits
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circuit. T designin analog c using 18 56.88% low volta range of
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A New Low-Voltage, Low-Power and High-Slew Rate CMOS Unity-Gain Buffer
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Comparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits
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Analysis and Design of Hybrid 4 bit CLA Full Adder
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Performance Analysis of CMOS and GDI Comparators
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Fault Testing of CMOS Integrated Circuits Using Signature Analysis Method
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AVTS Approach To Digital CMOS Circuits For Diminishing Complete Power Expenditure
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THE DESIGN OF HIGH PERFORMANCE THREE INPUT XOR GATE BASED ON COMPOUND GATE METHODOLOGY
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Low Power Design Techniques in CMOS Circuits : A Review
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PMOS Testing at Rochester Institute of Technology Dr. Lynn Fuller
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Reduction of Leakage Power in CMOS circuits (Gates) using LC nMOS Technique
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Analysis of 16 bit carry look ahead adder A subthreshold leakage power perspective
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PVT Insensitive Reference Current Generation
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16*16 BIT LOW POWER HIGH SPEED FIXED POINT MULTIPLIERJasbir Kaur* & Dr. Neelam Rup Prakash
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