Fault Coverage
An Optimal Machine Learning approach for Fault Coverage Improvement on Silicon Through Functional Testcases
... maximum fault coverage with the functional test cases of lesser test run time with the constraint of limited tester memory ...maximum fault coverage with less number of test ...maximum ...
5
Implementation of UART with BIST Technique for High Fault Coverage M Priyanka & A Chandrakala
... 2. Pseudo exhaustive Testing: Pseudo exhaustive test- ing divides the CUT into several smaller sub circuits and tests each of them exhaustively. All detectable flaws within the sub circuits can be detected. However, such ...
5
Efficient Implementation of Fault Coverage Circuit for High Speed and Low Power Applications
... This microprocessor is unique in the fact that its 1.4 Billion transistor count, capable of a teraflop of performance, is almost entirely dedicated to logic (Itanium's transistor count is largely due to the 24MB L3 ...
6
Enhancing delay fault coverage through low power segmented scan
... high fault coverage for delay faults as, for example, for stuck-at ...delay fault coverage, enhanced scan which allows application of arbitrary two-pattern tests has been proposed ...the ...
17
Fault Coverage Circuit architecture using efficient Hardware for Testing Applications Krishna Chaitanya & K Bindu Madhavi
... A new low power BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation. The proposed low power/energy BIST technique is based on a modified clock scheme for ...
10
An Efficient Reversible PLA Implemented In BIST for More Fault Coverage
... input can be reconstructed from output. Like conventional circuits, the reversible circuits should also be protected from faults. Depending on their detection time, these approaches have been categorized into offline and ...
8
A new method for improving path delay fault coverage
... First only those rows are chosen that for some column(s), there is only one '1' in that column and the chosen row. Then, all the columns that have one '1' on the row should be chosen. In other words, all the two-piece ...
8
Low Power and High Fault Coverage BIST TPG
... Abstract: This paper presents a low hardware overhead test pattern generator (TPG) for scan-based Built-In Self-Test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve ...
7
FAULT TOLERANT DEFLECTING ROUTER WITH HIGH FAULT COVERAGE FOR ON-CHIP NETWORK
... The different methods used to eliminate transient faults are ARQ, FEC and hybrid ARQ and the algorithms for avoiding permanent faults are cost based routing algorithm and fault on neighbor aware routing algorithm. ...
8
SEDSR: Soft Error Detection Using Software Redundancy
... The mentioned methods are widely used for control flow and data errors detection. These methods are eva- luated and compared with each other by fault injection. As mentioned, by the technology progress and ...
7
3-Weight Pseudo-Random Test Set Generation For Combinational Circuits
... applied for faults that could not be detected otherwise (if such faults remain). The method can thus be viewed as a weighted random test generation method that uses three weights: a weight of 0.5 indicates pure random ...
5
Two Pattern Test Cubes for Transition Path Delay Faults Test for ISCAS-85 C432
... stuck-at fault is a particular fault model used by fault simulators and automatic test pattern generation (ATPG) tools to mimic a manufacturing defect within an integrated ...stuck-at fault ...
7
Universal Pattern Set for Arithmetic Circuits
... various fault models of different test pattern set size and variant hardware requirement have been ...High fault coverage of multipliers is achieved with Cell Fault Model ...
5
THE NON-SCAN DELAY TEST ENRICHMENT BASED ON RANDOM GENERATED LONG TEST SEQUENCES
... transition fault coverages than tests produced by deterministic ATPG ...the fault coverage of the initial ran- dom generated test sequence, minimizing the length of the test by eliminating ...
6
Practical Considerations in Oscillation Based Test of SC Biquad Filters
... the fault coverage results obtained in the case study of OBT of a low- pass SC biquad, where the filter stage was transformed into a quadrature oscillator by internal SC stage reconfiguration ...64% ...
9
SOFTWARE CONFIGURATION MANAGEMENT PRACTICE IN MALAYSIA
... of fault-detection ...Path coverage, fault coverage and statement coverage, whereas the most of the other researches only compares maximum two or three objective criteria on their ...
8
Fault-Tolerant Nanosatellite Computing on a Budget
... strong fault coverage with commodity ...facilitating fault tolerance based upon thread-level coarse-grain lockstep, which we validated through ...long-term fault coverage, our ...
8
Low-Cost Concurrent Error Detection for GCM and CCM
... its fault coverage is around ...permanent fault [17]. It also provides provable security against fault attacks ...the fault coverage of the proposed scheme can detect permanent ...
19
Design and Implementation an Efficient Hardware Utilization for Testing Applications by UART with BIST
... combinational circuits while attaining high fault coverage. Test time and area overhead remain unaffected. Another low-power test pattern generator based on a modified LFSR is proposed in. The scheme ...
9
Adaptive Test Pattern Generation Using BIST Schemes
... The design methodology is circuit-specific and uses synthesis techniques to design BIST generators [15]. The pattern generator consists of two components: a pseudorandom pattern generator like an LFSR and a ...
9