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Pull-up

Management algorithm for failed gastric pull up reconstruction of laryngopharyngectomy defects: case report and review of the literature

Management algorithm for failed gastric pull up reconstruction of laryngopharyngectomy defects: case report and review of the literature

... The patient was then taken to the operating room and found to have circumferential necrosis of the proximal GPU extending inferiorly into the upper mediastinum (Fig. 1a). The necrosis was debrided until well-vascularized ...

9

Retrograde stapling of a free cervical jejunal interposition graft: a technical innovation and case report

Retrograde stapling of a free cervical jejunal interposition graft: a technical innovation and case report

... the pull-up gastric interposition was per- formed after gastroscope insertion via the distal part of the gastric conduit (Figure ...gastric pull-up conduit (Figure 3B) and the OrViL® delivery ...

6

Scheming Of 4-Bit Cmos Arithmetic Logic Unit Using Efficient Logic Techniques

Scheming Of 4-Bit Cmos Arithmetic Logic Unit Using Efficient Logic Techniques

... The redesign is carried out by removing the redundant branches from DPL structure. It was carried out mostly by considering the pull up and pull down transition times in the resulting structure by ...

8

Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits

Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits

... Another important technique (named Sleepy Keeper), depicted in Figure 2(b), can reduce leakage power like MTCMOS and exploits keeper transistors in parallel to pull up and pull down switch ...

5

AN EFFICIENT ADIABATIC FULL ADDER DESIGN APPROACH FOR LOW POWER

AN EFFICIENT ADIABATIC FULL ADDER DESIGN APPROACH FOR LOW POWER

... The pull up network is designed with combination of NMOS and PMOS.When the inputs a, b and c are at logic 011 and V DD move up from lower position to higher position of cons[r] ...

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Design and Development of Solar based Power Maximization using Solar Tracking System

Design and Development of Solar based Power Maximization using Solar Tracking System

... Port A (PA7..PA0): Port A serves as the analog inputs to the A/D Converter. Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up ...

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Volume 28, Number 5 (September 1975)

Volume 28, Number 5 (September 1975)

... Dormant-season grazing of Sherman big bluegrass was effective in reducing “pull up.” As evidenced by aggregation of big bluegrass and minor invasion by native spe[r] ...

105

Trim and Maneuverability Analysis Using a New Constrained PSO Approach of a UAV

Trim and Maneuverability Analysis Using a New Constrained PSO Approach of a UAV

... Performance characteristic of an Unmanned Air Vehicle UAV is inves- tigated using a newly developed heuristic approach. Almost all ight phases of any air vehicle can be categorized into trim and maneuvering ights. In ...

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Volume 4, Issue 7, 2018

Volume 4, Issue 7, 2018

... Given the effects of dynamic core and static core exercise of 10 weeks applied to child athletes participating in the study, it has been observed that there are differences in the values of standing long jump of dynamic ...

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Volume 5, Issue 1, 2018

Volume 5, Issue 1, 2018

... by Pull-Up Test, Running Speed was measured by 20-Meter Dash, Running Agility was measured by Illinois Agility Test, Jumping Ability was measured by Standing Long Jump Test, Throwing Ability was measured by ...

8

Finite Element Analysis of High Frequency Breaker Vibrator

Finite Element Analysis of High Frequency Breaker Vibrator

... Based on the above allowable stress values and stress analysis results, there is no risk of material failure in the stress concentration zones of the rapiter assem- bly pull-up bracket and pull-down ...

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A LITERATURE REVIEW ON A LOW-POWER SINGLE-PHASE CLOCK MULTIBAND FLEXIBLE DIVIDER

A LITERATURE REVIEW ON A LOW-POWER SINGLE-PHASE CLOCK MULTIBAND FLEXIBLE DIVIDER

... Available Online at www.ijpret.com 199 Figure.2.Proposed dynamic logic multiband flexible divider using sleep transistor B). Dual Stack Approach In dual stack approach [7], 2 PMOS in the pull- down network and 2 ...

7

Volume 4, Issue 8, 2018

Volume 4, Issue 8, 2018

... by Pull-Up Test, Running Speed was measured by 20-Meter Dash, Running Agility was measured by Illinois Agility Test, Jumping Ability was measured by Standing Long Jump Test, Throwing Ability was measured by ...

10

Low Power Based Dual Mode Logic Gates using Power Gating Technique

Low Power Based Dual Mode Logic Gates using Power Gating Technique

... extra pull up and two extra pull down transistors in sleep mode either in OFF state or in ON ...the pull down NMOS transistor is in ON state and in the pull up network the PMOS ...

6

Reduction of Leakage Power in CMOS circuits (Gates) using LC nMOS Technique

Reduction of Leakage Power in CMOS circuits (Gates) using LC nMOS Technique

... either pull-up or pull-down or both the networks from supply voltage or ground or both using sleep ...between pull-up networks and Vdd and pull down networks and Gnd while for ...

7

Low Power Energy Efficient Level Shifter in Multi supply Voltage Design

Low Power Energy Efficient Level Shifter in Multi supply Voltage Design

... self-adapting pull-up network to increase switch speed and to reduce dynamic energy consumption, and a split input inverting buffer is used at the output stage to improve energy ...can up-convert ...

5

The physics of unwound and wound strings on the electric guitar applied to the pitch intervals produced by tremolo/vibrato arm systems

The physics of unwound and wound strings on the electric guitar applied to the pitch intervals produced by tremolo/vibrato arm systems

... An American made Fender Stratocaster was used for the measurements presented here (Oiled Ash 10 for 15 limited edition). This instrument has the American standard two post Fender Stratocaster tremolo system with a 9.5 ...

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Low Power and Area Efficient Design of VLSI Circuits

Low Power and Area Efficient Design of VLSI Circuits

... the pull up and pull down networks,which is placed in a path from pull down network to ground which provides the additional resistance thereby reducing the leakage current in the path from ...

5

LCPMOS : An Area Efficient Leakage Power Reduction In CMOS Circuits

LCPMOS : An Area Efficient Leakage Power Reduction In CMOS Circuits

... either pull-up or pull-down or both the networks from supply voltage or ground or both using sleep ...between pull-up networks and Vdd and pull-down networks and gnd while for ...

5

Balanced XOR/XNOR Circuits using CNTFET

Balanced XOR/XNOR Circuits using CNTFET

... of pull up and pull down networks are used to eliminating the critical states of a circuit ...use pull up and pull down ...

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