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serial in parallel out

Digit-Level Serial-In Parallel-Out Multiplier Using Brent Kung Adder

Digit-Level Serial-In Parallel-Out Multiplier Using Brent Kung Adder

... level Serial-In Parallel Out multiplier using Parallel Adder which concentrates on gate levels to improve the speed and decreases the ...

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Dynamics Analysis of 2PPPPS R 2PPPPS Serial Parallel Mechanism

Dynamics Analysis of 2PPPPS R 2PPPPS Serial Parallel Mechanism

... Abstract. In this paper, the stress condition of each hinge point of the new 2PPPPS-R-2PPPPS serial-parallel mechanism is analyzed comprehensively by establishing dynamic equations and Euler equations. ...

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Parallel and Serial Concatenated Single Parity Check Product Codes

Parallel and Serial Concatenated Single Parity Check Product Codes

... Parallel and serial concatenated SPC product codes are very simple to encode and decode. Furthermore, their perfor- mance is reasonably good when compared to the sphere- packing bound. Three-dimensional ...

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A Geometric Approach to the Design of Serial and Parallel Manipulators with Passive Joints

A Geometric Approach to the Design of Serial and Parallel Manipulators with Passive Joints

... on serial and parallel manipulators when external forces are ...For parallel manipulators, joint failure may or may not allow a motion generated by the passive ...for serial manipulators joint ...

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Analysis and Optimization of a Spatial Parallel Mechanism for a New 5-DOF Hybrid Serial-Parallel Manipulator

Analysis and Optimization of a Spatial Parallel Mechanism for a New 5-DOF Hybrid Serial-Parallel Manipulator

... of parallel mechanisms (PMs), PMs have been studied widely, mainly because of PMs owning the characteristics of compact structure, high stiffness, and high load capacity compared with serial mechanisms [1, ...

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Singular Kinetics Analysis of Cartesian Serial Parallel Manipulator

Singular Kinetics Analysis of Cartesian Serial Parallel Manipulator

... traditional serial and parallel machine tools, a Cartesian serial-parallel manipulator is constructed, it has a good comprehensive performance, but because of the special structure of the ...

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A NOVEL DESIGN OF REVERSIBLE SERIAL AND PARALLEL ADDER/SUBTRACTOR

A NOVEL DESIGN OF REVERSIBLE SERIAL AND PARALLEL ADDER/SUBTRACTOR

... reversible parallel adder/subtractor using 4*4 Reversible DKG gate that can work singly as a reversible full adder and a full ...A serial adder/subtractor is also designed in this paper using Reversible ...

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SERIAL COMPUTING vs. PARALLEL COMPUTING: A COMPARATIVE STUDY USING MATLAB

SERIAL COMPUTING vs. PARALLEL COMPUTING: A COMPARATIVE STUDY USING MATLAB

... Abstract— parallel computing has been around for many years but it is only recently that interest has grown due to the introduction of multi core processor at a reasonable price for the common ...compare ...

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Serial and Parallel Bayesian Spam Filtering using Aho Corasick and PFAC

Serial and Parallel Bayesian Spam Filtering using Aho Corasick and PFAC

... between serial execution and parallel execution. Parallel execution takes less than 2 seconds to execute larger data sets where as for same data set serial execution takes more than 10 ...that ...

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Compact Qca Based Serial-Parallel Multiplier For Signal Processing Applications

Compact Qca Based Serial-Parallel Multiplier For Signal Processing Applications

... the serial-parallel multiplier leads to ...multilayer serial parallel multiplier in [9] and ...coplanar serial-parallel multiplier. Hence the proposed serial ...

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Designing of Parallel to Serial Converter and Flash ADC using Reversible Gate

Designing of Parallel to Serial Converter and Flash ADC using Reversible Gate

... Traditional parallel link has been used in circuits for a long time, which let the data be sent over multiple channels ...A Serial Data link is preferred for long distance ...of parallel to ...

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PARALLEL AND SERIAL CONTROL STRATEGIES OF IMAGE UNDERSTANDING

PARALLEL AND SERIAL CONTROL STRATEGIES OF IMAGE UNDERSTANDING

... massively parallel computing hardware. Parallel distribution of image file reduces the complexity and increase the capability of image ...represent serial parallel control strategies to handle ...

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A competent reversible logic SIPO serial 
		to parallel converter in QCA technology

A competent reversible logic SIPO serial to parallel converter in QCA technology

... based serial to parallel converter is developed using Quantum cellular automata ...SIPO serial to parallel converter has been realized using the proposed D Flip ...

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Inefficiency of orientation averaging: evidence for hybrid serial/parallel temporal integration

Inefficiency of orientation averaging: evidence for hybrid serial/parallel temporal integration

... Intuition suggests that increased viewing time should allow for the accumulation of more visual information, but scant support for this idea has been found in studies of voluntary averaging, where observers are asked to ...

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Parallel Intersection and Serial Composition of Finite State Transducers

Parallel Intersection and Serial Composition of Finite State Transducers

... Parallel Intersection and Serial Composition of Finite State Transducers P a r a l l e l I n t e r s e c t i o n a n d S e r i a l C o m p o s i t i o n o f F i n i t e S t a t e T r a n s d u c e r s[.] ...

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Serial to Parallel Code Converter Tools: A Review

Serial to Parallel Code Converter Tools: A Review

... 5. Polaris compiler: Polaris is an automatic parallelization tool for FORTRAN programs. The objective of Polaris compiler is automatic code parallelization and to create and preserve the optimizing compiler. The compiler ...

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An Area Efficient With Serial-In Parallel-Out By Using Rb Multiplier

An Area Efficient With Serial-In Parallel-Out By Using Rb Multiplier

... Digit serial RB multiplication in a bit level matrix vector form is most efficient in terms of area-time ...find out new methods to obtain partial products in lesser time and with less hardware ...

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Design and Analysis of High Performance Double Edge Triggered D-Flip Flop based Shift Registers

Design and Analysis of High Performance Double Edge Triggered D-Flip Flop based Shift Registers

... of Serial In Serial Out (SISO), Serial In Parallel Out (SIPO), Parallel In Serial Out (PISO) and Parallel In Parallel Out (PIPO) shift ...

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Brief Introduction about VHDL Implementation of CVSD Codec Neha Sharma, Amrita Soni, Piyush Gupta

Brief Introduction about VHDL Implementation of CVSD Codec Neha Sharma, Amrita Soni, Piyush Gupta

... in parallel out) for detecting slope overload, 8 bit PIPO (parallel in parallel out) for providing 1 clock cycle delay , overload detect and level select algorithm is used for selecting ...

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Improve performance of PIPO (Parallel in Parallel Out) Shift Register by use Transistor Gating Technique

Improve performance of PIPO (Parallel in Parallel Out) Shift Register by use Transistor Gating Technique

... as Serial In - Serial Out, Serial In - Parallel Out, Parallel In – Serial Out, Parallel In - Parallel Out, and bidirectional shift ...

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