Sub-Threshold Leakage
A New Enhanced Delayed Lock Loop Design Using Stand By Switch For Reduced Sub-Threshold Leakage Current
12
EFFICIENT DESIGN OF CMOS CIRCUITS USING NEW REVERSE BODY BIASED TECHNIQUE IN DOMINO LOGIC FOR SUB THRESHOLD LEAKAGE REDUCTION
9
"Leakage Current Reduction Causes Due to Sub-Threshold Conduction in Parasitic p-n Junction"
9
Novel Subthreshold and Gate Leakage Reduction Techniques for 6T-SRAM Cell
7
An Efficient Ultra Low Power Circuit by Using Subthreshold Adiabatic Logic
5
Analysis of Leakage Current Reduction Techniques in SRAM Cell in 90nm CMOS Technology
5
Design of Low Power Full Adder Using ONOFIC Approach
6
Performance Analysis of Adiabatic 6T SRAM and Bulk-Biased 6T SRAM
5
Design of a Low Voltage Class-AB CMOS Super Buffer Amplifier with Sub Threshold and Leakage Control
5
Static Noise Margin Analysis of Various SRAM Topologies
6
A New Technique for Leakage Reduction in DSM Technology
8
Multi Threshold Low Power SRAM Using Floating Gates
7
Leakage Power Reduction Techniques for Nanoscale CMOS VLSI Systems and Effect of Technology Scaling on Leakage Power
7
SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey
31
Low Leakage Multi Threshold Level Shifter Design using Sleepy Keeper
6
Performance Optimization of Low Leakage and Low Power 8T SRAM Cell Sandhya Patel *1 , Somit Pandey 2
5
Noise Tolerant Circuits for Modified Feedthrough Logic
6
Design Of Low Power Cmos Adder, Serf, Modified Serf Adder
10
AN ANALYTICAL APPROACH TO DESIGN A POWER-EFFICIENT SINGLE-PORT CONVENTIONAL SRAM BIT-CELL FOR MOBILE/MULTIMEDIA APPLICATIONS
9
Galeorstack A Novel Leakage Reduction Technique for Low Power VLSI Design
9