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Sub-Threshold Leakage

A New Enhanced Delayed Lock Loop Design Using Stand By Switch For Reduced Sub-Threshold Leakage Current

A New Enhanced Delayed Lock Loop Design Using Stand By Switch For Reduced Sub-Threshold Leakage Current

... Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors ...

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EFFICIENT DESIGN OF CMOS CIRCUITS USING NEW REVERSE BODY BIASED TECHNIQUE IN DOMINO LOGIC FOR SUB THRESHOLD LEAKAGE REDUCTION

EFFICIENT DESIGN OF CMOS CIRCUITS USING NEW REVERSE BODY BIASED TECHNIQUE IN DOMINO LOGIC FOR SUB THRESHOLD LEAKAGE REDUCTION

... the threshold voltage thereby reducing the sub threshold leakage ...the threshold voltage is increased through body biasing, sub threshold leakage ...to ...

9

"Leakage Current Reduction Causes Due to Sub-Threshold Conduction in Parasitic p-n Junction"

"Leakage Current Reduction Causes Due to Sub-Threshold Conduction in Parasitic p-n Junction"

... The sub- threshold leakage control techniques that do not adversely affect the circuit performance and layout ...reduced sub-threshold leakage compared to a single off ...reduce ...

9

Novel Subthreshold and Gate Leakage Reduction Techniques for 6T-SRAM Cell

Novel Subthreshold and Gate Leakage Reduction Techniques for 6T-SRAM Cell

... the sub-threshold leakage in the SRAM ...the leakage current. As we know each transistor has different leakage components in standby mode the same analysis should be carried out as in ...

7

An Efficient Ultra Low Power Circuit by Using Subthreshold Adiabatic Logic

An Efficient Ultra Low Power Circuit by Using Subthreshold Adiabatic Logic

... explained sub threshold logic, circuits operated with the power clock Vdd, below than the threshold voltage (Vth) of the transistor, and it employ the sub threshold leakage ...

5

Analysis of Leakage Current Reduction Techniques in SRAM Cell in 90nm CMOS Technology

Analysis of Leakage Current Reduction Techniques in SRAM Cell in 90nm CMOS Technology

... on leakage current minimization in single static random access memory (SRAM) cell in 90nm complementary metal oxide semiconductor (CMOS) ...The leakage current mainly consists of sub threshold ...

5

Design of Low Power Full Adder Using ONOFIC Approach

Design of Low Power Full Adder Using ONOFIC Approach

... 3) Leakage current. The leakage current consists of reverse-bias diode currents and sub threshold ...drain leakage and gate direct tunneling leakage have become the significant ...

6

Performance Analysis of Adiabatic 6T SRAM and Bulk-Biased 6T SRAM

Performance Analysis of Adiabatic 6T SRAM and Bulk-Biased 6T SRAM

... to leakage current is one of the major ...the sub threshold leakage current and average power consumption bulk bias technique is used and the optimum value of bulk bias is applied only to the ...

5

Design of a Low Voltage Class-AB CMOS Super Buffer Amplifier with Sub Threshold and Leakage Control

Design of a Low Voltage Class-AB CMOS Super Buffer Amplifier with Sub Threshold and Leakage Control

... transistor threshold voltage (Vth) has to be commensurately scaled to maintain a high drive current and achieve the performance ...the threshold voltage scaling results in the substantial increase of the ...

5

Static Noise Margin Analysis of Various SRAM Topologies

Static Noise Margin Analysis of Various SRAM Topologies

... the sub-threshold leakage due to its exponential relation to the threshold voltage, and gate leakage due to the reducing gate-oxide ...the leakage current, the supply voltage is ...

6

A New Technique for Leakage Reduction in DSM Technology

A New Technique for Leakage Reduction in DSM Technology

... of threshold voltage results in exponential increase of the sub-threshold leakage current ...and threshold voltage scaling trends for Intel’s microprocessor process technologies are ...

8

Multi Threshold Low Power SRAM Using Floating Gates

Multi Threshold Low Power SRAM Using Floating Gates

... This thesis work focuses on reduction of static power using combine of stack and multi threshold voltage principle. Figure 1 shows the structure of stack approach. When more than one transistor in the stack is ...

7

Leakage Power Reduction Techniques for
Nanoscale CMOS VLSI Systems and Effect of
Technology Scaling on Leakage Power

Leakage Power Reduction Techniques for Nanoscale CMOS VLSI Systems and Effect of Technology Scaling on Leakage Power

... this leakage power ...[6]. Leakage current has become a primary concern for low-power, highperformance digital CMOS ...the leakage component of the total chip power can be attributed to ...

7

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

... Sub-threshold leakage rises by ten times for every ...to threshold variation at lower supplies [8] [9] ...down, leakage current in a sub-micron region becomes more significant ...

31

Low Leakage Multi Threshold Level Shifter Design using Sleepy Keeper

Low Leakage Multi Threshold Level Shifter Design using Sleepy Keeper

... The diode-connected MP7 device minimizes the leakage current, also by increasing the threshold voltage of MP5. In fact, MP7 causes the source of transistor MP5 to be at lower voltage than the bulk node and ...

6

Performance Optimization of Low Leakage and Low Power 8T SRAM Cell Sandhya Patel *1 , Somit Pandey 2

Performance Optimization of Low Leakage and Low Power 8T SRAM Cell Sandhya Patel *1 , Somit Pandey 2

... below, Leakage current and leakage power and sub-threshold leakage current has been primary challenges for SRAM design and ...low leakage and low power 8T SRAM ...the ...

5

Noise Tolerant Circuits for Modified Feedthrough Logic

Noise Tolerant Circuits for Modified Feedthrough Logic

... the sub-threshold leakage current, the inverter designed by stacked transistor technique is more robust than LP-FTL ...the leakage power and ANTE comparison for the ...

6

Design Of Low Power Cmos Adder, Serf, Modified Serf Adder

Design Of Low Power Cmos Adder, Serf, Modified Serf Adder

... Sub threshold circuit design involves scaling the supply voltage below the threshold voltage, where load capacitances are charged/discharged by sub threshold leakage ...currents. ...

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AN ANALYTICAL APPROACH TO DESIGN A POWER-EFFICIENT SINGLE-PORT CONVENTIONAL SRAM BIT-CELL FOR MOBILE/MULTIMEDIA APPLICATIONS

AN ANALYTICAL APPROACH TO DESIGN A POWER-EFFICIENT SINGLE-PORT CONVENTIONAL SRAM BIT-CELL FOR MOBILE/MULTIMEDIA APPLICATIONS

... various leakage reduction techniques available for different leakage mechanisms, ...Tunneling-Leakage, Sub-threshold Leakage, Reverse Bias Source/Drain Junction Leakage, ...

9

Galeorstack  A Novel Leakage Reduction Technique for Low Power VLSI Design

Galeorstack A Novel Leakage Reduction Technique for Low Power VLSI Design

... and threshold voltage have been scaling down for decades in order to achieve high ...and threshold voltage increases sub threshold leakage ...increases sub threshold ...

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