[PDF] Top 20 Generic Low-Latency Masking in Hardware
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Generic Low-Latency Masking in Hardware
... nm Low-K UMC process with 1 V supply and a 20 MHz clock synthesized with the Cadence Encounter RTL compiler ...the low-latency designs are given in Table 1. The design is generic in terms of ... See full document
21
Reliable Low-Latency and Low-Complexity Viterbi Architectures Benchmarked on ASIC and FPGA
... We have utilized RESO which performs the recomputation step with shifted operands, i.e., all operands are shifted left or right by k bits (this method is efficient in detecting k consecutive logic errors and k − 1 ... See full document
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A Mechanism Achieving Low Latency for Wireless Datacenter Applications
... HULL [11] does not employ a scheduling mechanism, but trades a little bandwidth to reduce the latency of short flows. It leverages Phantom Queues to get congestion informa- tion in advance. The end hosts make use ... See full document
20
A MODIFIED ARCHITECTURE DESIGN FOR ADVANCE ENCRYPTION STANDARD WITH ENHANCEMENT IN MIX COLUMNS FOR SECURE DATA USAGE
... In this paper we are presenting an encryption algorithm called Advance Encryption Standard .We have designed AES algorithm using Verilog HDL and in this design we have used look up table substitution for byte in state ... See full document
6
Generic Hardware Architectures for Sampling and Resampling in Particle Filters
... for low sample rates. The FPGA hardware SIRF on the other hand can pro- cess input samples at rates of upto ...the hardware realization of the SIRF not only allows for increased sample rates but also ... See full document
15
Low Latency Low Complexity Compare and Decode Architecture for LTE Turbo Codes
... The Viterbi-Algorithm (VA) is a common application of dynamic programming. Since it contains a nonlinear feedback loop (ACS-feedback, ACS: add-compare-select), this loop is the bottleneck in high data rate ... See full document
5
Arithmetic Addition over Boolean Masking - Towards First- and Second-Order Resistance in Hardware
... In this paper, we present two design strategies to realize a secure and efficient arithmetic adder for Boolean-masked values. First, we introduce an architecture based on the ripple-carry adder that targets ... See full document
20
Masking the AES with Only Two Random Bits
... in hardware masking, there exist more online randomness efficient S-box implementations which, however, require an increased amount of input shares for the S-box ...the latency with reset cycles ... See full document
28
Efficient Low Bit Rate Low Latency Channelization in DECT
... DECT, low bit-rate transmission is feasible either at the cost of efficiency (shorter slots with fixed overhead per slot) or increased latency (longer ...for low bit-rate low-latency ... See full document
8
Article Minimising latency of pitch detection algorithms for live vocals on low-cost hardware
... the latency of pitch detection algorithms and methods with which this can be ...further latency challenge that is sparsely studied, minimising the length of sampled audio required by the algorithms in order ... See full document
21
Glitch-Resistant Masking Revisited - or Why Proofs in the Robust Probing Model are Needed
... higher-order masking in hardware, mixing engineering intu- itions and elements borrowed from the software-oriented masking ...Consolidated Masking (CMS) scheme in [41, 12], the Domain-Oriented ... See full document
41
SHIM and Its Applications
... our latency-sensitive workload, we use the widely deployed Apache Lucene open-source search engine [Apache Lucene, ...percentile latency SLO. Elfen improves core utilization by 90% at low load and ... See full document
134
3PC ORAM with Low Latency, Low Bandwidth, and Fast Batch Retrieval
... Brief Overview of our 3PC ORAM. We sketch the main ideas behind our 3PC protocol that emulates Circuit-ORAM ORAM. Observe that Circuit-ORAM client, like a client in any Binary-Tree ORAM variant, performs the following ... See full document
45
Low Randomness Masking and Shuffling: An Evaluation Using Mutual Information
... a low-randomness version of the standard Boolean masking schemes, namely it introduces Recycled Randomness Masking ...describe generic RRM schemes (Section ... See full document
22
Masking Large Keys in Hardware: A Masked Implementation of McEliece
... The masked design is implemented in VHDL and is synthesized for Xilinx Virtex-5 XC5VLX50 FPGA which holds the crypto engine in the side channel evaluation board SASEBO-GII. The implementation results are listed in Table ... See full document
15
A Low-Latency, Low-Area Hardware Oblivious RAM Controller
... An important use case for ORAM is in trusted hard- ware [15], [7], [21], [22], [19], [6]. Figure 1 shows an example target cloud configuration. Here, a client communicates with a trusted secure cloud processor that is ... See full document
8
Rhythmic Keccak: SCA Security and Low Latency in HW
... in hardware. Several masking schemes have been proposed in the literature that provide security even in the presence of ...for low-latency ... See full document
22
Consolidating Security Notions in Hardware Masking
... example low entropy masking ...investigating low entropy masking for hardware is an interesting direction for future ...multiplicative masking, since it is well known that a ... See full document
29
Multiplicative Masking for AES in Hardware
... earliest masking schemes [GP99, Tri03, ISW03] were shown to be unsuitable for hardware implementations by Mangard et ...to low-level routing details and a careful char- acterization of the logic ... See full document
39
Design of Area Efficient Low Latency Sorting Units
... In the past, the major concerns of the vlsi were area, performance, cost and reliability. The sorting problem has been investigated under various parallel architectures, since utilizing many functional units to sort ... See full document
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