The half bridge inverters can keep the common mode voltage constant, but the dc voltage utilization of half bridge type topology is half of full bridge topology is half of full bridge topology. In order to this, either large number of PV panels in series are involved or boost dc/dc converter with extremely high voltage transfer ratio is required as the first power conditioning stage, which could decrease the system efficiency. So many solutions have been proposed to realize the common mode voltage constant in the full bridge transformerless inverters. A traditional method is to apply full bridge inverter with bipolar sinusoidal PWM. The common mode voltage is kept constant during all operating modes. So it has excellent leakage current characteristics. But the current ripples across the filter inductors and also switching losses are likely to be large. So unipolar SPWM is preferred over bipolar SPWM because of excellent differential mode (DM) characteristics such as smaller inductor current ripple and higher conversion efficiency. But the common mode voltage of the conventional unipolar SPWM varies at the switching frequency, which leads to high leakage currents (Madhuri Kshirsagar and Shah, 2016; Madhuri Kshirsagar and Shah, 2016). Without transformer there is a galvanic connection between grid and PV array which forms resonant circuit and induce common mode leakage current (Twining and Holmes, 2003; Kjaer et al., 2005). The simplified equivalent model of common mode leakage current has been derived is as shown in fig. 1, C pv is the parasitic capacitance, L A and L B are filter
dc–dc stage. The full-bridge topology requires half of the input voltage demanded by the half-bridge topology, that is, around 350 V for European applications. In order to avoid a varying common-mode voltage, the full bridge has to be modulated with bipolar PWM, a modulation strategy that leads the converter to a low efficiency and a high current ripple . In this paper, an improved grid-connected inverter topology for transformerless PV systems is presented, which can sustain the same low input voltage as the full-bridge inverter and guarantee not to generate the common- mode leakage current.
In order to minimize the leakage current through the parasitic capacitance of the PV array and improve the efficiency, several techniques have been used,. One method is to use Half-bridge or Neutral point clamped (NPC) topology where in the midpoint of the dc-link capacitors is connected to the grid neutral. These topologies depict very high efficiencies. But its disadvantage is requirement for a high input-voltage level or else a boost stage. Another method is to separate the PV panel from the grid for H-bridge inverters, when zero voltage is applied to the grid. The separation can be on either on dc side of the inverter or its ac side. Example for dc decoupling schemes are like the H5 topology, and ac decoupling scheme is like Highly Efficient and Reliable Inverter Concept (HERIC) topology.
Abstract: grid feeding solar photovoltaic (PV) inverters to suppress the second harmonic and switching frequency voltage ripples. With aging equivalent series resistance (ESR) of capacitor increases and its capacitance value decreases, which lead to increase in dc-link voltage ripple Oscillations in PV operating point around its maximum power point (MPP), results in reduction of average output power and revenue generated. To address this, frequent replacement of capacitors are required, which may lead to increased cost. Therefore, capacitors must be replaced at an optimal period to ensure maximum earnings. To realize this, a technique for monitoring of power extraction efficiency (PEE) is proposed in this paper. Further, criteria for replacement of capacitor based on the measured values of PEE are suggested. Mathematical model relating the capacitance and ESR values to the PEE is derived. Effect of variation in temperature and solar radiation on PEE isdiscussed. Detailed simulation studies are carried out usingMATLAB-Simulink. A scaled down laboratory prototype of inverter is developed. The proposed technique is implemented in the existing digital processor/controller used forMPP tracking, thereby avoiding additional circuits/sensors.PEE estimated by simulation and experimentation arefound to be within 1% of each other.
Abstract: Renewable energy sources are getting more and more widespread, mainly due to the fact that they generate energy by keeping the environment clean. Most of these systems have an isolation transformer included, which if excluded from the system would increase the efficiency and decrease the size of PV installations, furthermore it would lead to a lower cost for the whole investment. For safety reasons grid connected PV systems include galvanic isolation. In case of transformerless inverters, the leakage ground current through the parasitic capacitance of the PV panels, can reach very high values. A common-mode model based on analytical approach is introduced, used to predict the common- mode behavior, at frequencies lower than 50kHz, of the selected topologies and to explain the influence of system imbalance on the leakage current. It will be demonstrated that the neutral inductance has a crucial influence on the leakage current method.
Another solution is to disconnect the PV arrayfrom the grid, in the case of H-bridge (HB)inverters, when the zero vector is applied to theload (grid). This disconnection can be doneeither on the dc side of the inverter (like thetopology from and H5 topology from SolarTechnologies AG) or on the ac side (like theHighly Efficient and Reliable Inverter Concept(HERIC) topology from Sun ways).A new topology called HB zero-voltage staterectifier (HB- ZVR) is given where the midpointof the dc link is clamped to the inverter onlyduring the zero-state period by means of a dioderectifier and one switch. The aim of the work presented in this paper is tointroduce a common-mode model based onanalytical approach for the single phasephaseinverter connected to the utility grid with thehelp of NPC multi level inverter. This modelwill be used to predict the common-modebehavior, at frequencies lower than 50kHz, ofthe selected topologies and to explain theinfluence of system imbalance on the groundleakage current. It will also be shown, that theneutral inductance has a crucial influence on thecommon mode behavior of the topology, therebydirectly influencing the ground leakage currentof the system. Simulation results will bepresented in case of the NPC topology in orderto validate the simulation model.
Many interesting single-phase topologies have been reported such as Heric, H5, H6, and so on. But they are limited to three-level inverters -. On the other hand, the multilevel inverters can decrease the voltage stress of dv/dt on switches and increase the output waveform quality -. However, few papers have been reported regarding eliminating the leakage current for the single- phase cascaded multilevel inverters. A significant contribution by Zhou and Li is the filter-based leakage current suppression solution for the single-phase cascaded multilevel PV inverter . But the topology-based solution is rarely discussed in literature, and needs further investigation.
galvanic isolation (transformer less solution) for this basic topology. Since the PWM strategy alone is not sufficient to maintain a low ground leakage current. As it will be described in the following, the proposed PWM strategy stretches the efficiency by using, for the two legs where PWM frequency switching does not occur, devices with extremely low voltage drop, such as MOSFETs lacking a fast recovery diode. In fact, the low commutation fre- quency of those two legs allows, even in a reverse con- duction state, the conduction in the channel instead of the body diode (i.e., active rectification). Insulated-gate bipo- lar transistors (IGBTs) with fast anti parallel diodes are required in the legs where high-frequency hard switch- ing commutations occur. In grid-connected operation, one full-bridge leg is directly connected to the grid neutral wire, whereas the phase wire is connected to the converter through an LC filter.
This study has successfully developed a high-efficiency isolated single-input multiple-output buck converter with step- down operational states, and this coupled-inductor-based converter was applied well to a single input power source plus two output terminals composed of an auxiliary battery module and a high-voltage dc bus. The experimental results reveal that the maximum efficiencies at the step-up state and the step-down state were measured to be 94% and 97%, respectively. The major contributions of the proposed converter are recited as follows:This topology adopts eight power switches to achieve the objectives of high-efficiency power conversion, electric isolation, bi-directional energy transmission, and various output voltage with different levels.The stray energy can be recycled by a clamped capacitor into the auxiliary battery module or high-voltage dc bus to ensure the property of voltage clamping. An auxiliary inductor is designed for providing the charge power to the auxiliary battery module and assisting the switch turned on under the condition of zero-voltage-switching (ZVS). The switch voltage stress at the step-up state is not related to the input voltage so that it is more suitable for a dc power conversion mechanism with different input voltage levels. The copper loss in the magnetic core can be greatly reduced as a full copper film with lower turns. This high-efficiency converter topology provides designers with alternative electric isolation choices for boosting a low-voltage power source to multiple outputs with different voltage levels, or reversely transmitting the energy of high-voltage dc bus efficiently. The auxiliary battery module used in this study also can be extended easily to other dc loads, even for different voltage demands, via the manipulation of circuit components design. The project can be extended into still more E-vehice devices to be connected. (at present we have connected 10 vehicles per phase). The control algorithms can be implemented as a micro controller based or DSP based systems. A hardware implementation of the full system may be worked out in future tenure of the project. The system may be implemented as a single chip system with SOC (system on chip) technology.
level inverters are used in high power and medium voltage applications, since 1975 and are gaining much attention due to numerous advantages like common mode voltage, operation at both fundamental and high switching frequency, drawing input current with low distortion, reduced phase eleven level transformerless grid-connected mode leakage current is minimised using a transient circuit and efficiency is improved by regulating flying capacitor voltage with suitable switching strategy. Simulation results show the effectiveness of the proposed topology.
With a large quantity of power devices and three cascaded stages structure for the silicon IGBT based SST, it suffers from low efficiency and large size. With the devel- opment of 15 kV level SiC power MOSFET, the SST topology can be simplified as in Figure 1.5 while still provides the interface between the existing 12 kVac (7.2 kVac L-N) istribution system and 120/240 Vac utility voltage with an extra 400 Vdc bus. Due to SiC power MOSFET’s low loss and high switching capability, the new SST will have reduced the size, weight and improved the efficiency. The 10A high voltage SiC MOSFET developed by Cree Inc. has a 150um epitaxial layer which is target for blocking 15kV. The prototype samples have been tested up to 13.5 kV, and it will be referred to as >13 kV MOSFET in this dissertation.
Grid connected Photo Voltaic convertors have been used quite abundantly in residential renewable energy solutions. These convertors conventionally comprise of a heavy and expensive grid frequency transformer which works as an interface between the grid and the convertor. Transformerless systems have been researched upon and have shown to be suitably effective in terms of efficiency, cost and weight but weigh down in terms of the quality of the output power, infesting the grid with dc current ,  and causing an increase in the ground leakage current , .The module and the frame along with the connection between neutral wire and ground leads to parasitic capacitance allowing AC leakage current . Apart from ground leakage current disturbing the power quality it also leads to electromagnetic interferences compromising the safety of the system. International regulations pose strict limit to this. Thus systems need to take care about this issue irrespective of the architecture on which they are built upon. The common mode voltage existing in full-bridge- based topologies leads to development of the ground leakage current, basically due to the frequency variation of the common mode voltage observed across the output . Lots of solutions have been proposed over the years regarding the mitigation of the harmonic content present in the common-mode voltage –. With the grid-frequency transformer out of the system, the only bulky part that remains is the filter which filters the output from high frequency switching components. Any reduction in the size of the filter leads to considerable reduction in cost and weight and leads to improvement in efficiency too. Multilevel invertors focus on this aspect and have found way into the recent commercial PV convertors. Multilevel convertors capable of synthesizing the output voltage using more number of levels score over the conventional two- and three-level convertors in terms of reduction in harmonic distortion and they also present an advantage of efficient
The transistors used for the switching purpose are either MOSFETs or IGBTs based on the switching frequency, and the voltage and current ratings of the converter. The output voltage of this converter can be kept constant by adjusting the duty cycle D, where duty cycle is defined for one pair of switches. This converter is mainly used in high power fuel cell applications. The main advantage of this topology is that transistor voltage and current stress are not high with this configuration. The full-bridge converter has small input and output current and voltage ripples. The efficiency of this topology is also high. The cost of full bridge is higher compared to other topologies because full bridge topology requires a complex control system and four switches. The equation of the Full bridge converter in terms of duty cycle is given below.
The structure of the MMC-based PV system is the same as that in Chapter 3. However, it has been introduced again for reference purposes. The MMC-based PV system is comprised of three legs that are associated with three phases of the grid. Each leg of the converter includes two arms namely upper and lower arms. The arms of the converter are formed by series connection of N submodules. Each submodule consists of one half- bridge dc-ac converter, n isolated dc-dc converters which are fed by their associated sets of series- and parallel-connected PV generators. The isolated dc-dc converter is assumed to be the dual active bridge (DAB) topology with a medium frequency isolation transformer. Each DAB converter controls the voltage of its associated PV generator to implement maxim power point tracking (MPPT). Due to the galvanic isolation provided by the DAB converters, it is possible to ground the negative pole of the PV generators that enables the alleviation of potential-induced degradation (PID) phenomenon . The dc-dc converter used to interface PV generators with the dc side of the half-bridge converter is required to have galvanic isolation. Consequently, any dc-dc topology which offers galvanic isolation and required power rating could be potentially used. The use of DAB converter is because of its practical implementations of up to 100 kW [86, 87]. Figure 5.1 and 5.2 show the structure of the MMC-based PV system and its submodules for reference purpose.
of technical challenges in grid-connected PV systems, among which flow of leakage currents is a major problem. In this project, H6 transformer less full- bridge inverter topology is connected with a INTERLEAVED BOOST CONVERTER. As the input supply from the PV module is low, this interleaved boost converter increases the efficiency of the input supply, thus the desired output range is obtained. One additional switch with conventional full H- Bridge and diode clamping branch make sure the disconnection of PV module from the grid at the freewheeling mode and a clamp the short circuited output voltage at the half of DC input voltage. Therefore, the common mode (CM) leakage current is minimized. Aforementioned transformer less topology is simulated that validates the effectiveness of the converter by Matlab / Simulink.
III. PROPOSED HIGHEFFICIENCY AND PV TRANFORMERLESS INVERTER TOPOLOGY The proposed transformerless PV inverter, which is composed of six MOSFETs switches (S1–S6), six diodes (D1–D6), and two split ac-coupled inductors L1 and L2 as shown in Fig.3. The diodes D1–D4 perform voltage clamping functions for active switches S1–S4. The ac-side switch pairs are composed of S5, D5 and S6, D6, respectively, which provide unidirectional current flow branches during the freewheeling phases decoupling the grid from the PV array and minimizing the CM leakage current. The proposed inverter topology divides the ac side into two independent units for positive and negative half cycle. In addition to the highefficiency and low leakage current features, the proposed transformerless inverter avoids shoot-through enhancing the reliability of the inverter.
A highefficiency LED (Light Emitting Diode) driver based on Buck converter, which could operate under a wide AC input voltage range (85 V - 265 V) and drive a series of high power LEDs, is presented in this pa- per. The operation principles, power loss factors of the LED driver in this study are analyzed and discussed in detail and some effective ways to improve efficiency are proposed through system design considerations. To verify the feasibility, a laboratory prototype is also designed and tested for an LED lamp which consists of 16 LUMILEDS LEDs in series. Experimental results show that a highefficiency of 92% at I o = 350 mA
The grid tied photovoltaic system suffers a great loss because the performance of the transformer present in the inverter. The cost of the transformer is high and the maintaince cost is also high. Therefore transformer less inverter are widely used in grid tied photovoltaic system, due to the benefits of achieving highefficiency and low cost. The sinusoidal pulse width modulation of full bridge transformer less inverters can achieve highefficiency by using metal oxide semiconductor field effect transistor. Various topology has been implemented for transformer less inverter, but in that there is a problem of loss and reverse recovery characteristics. In our paper we are going to implement the centre tapped H bridge transformer less inverter topology for grid tied photovoltaic system to avoid the losses and leakage current. A clamped branch is added in the transformer less inverter. The added clamping branch clamps the freewheeling voltage at the freewheeling period. As the common mode voltage is kept constant for the whole grid period that reduces the leakage current. The splitting structure of inductor at the region of grid side avoids reverse recovery voltage and this improves the efficiency of the system. The detailed analysis of our topology with the operational modes, leakage current analysis and design consideration were implemented.
Hard switching operation of active switches causes many problems in the circuit. This generates high switching losses and introduces high voltage and current stresses on circuit components. The circuit efficiency and stability decreases. In the proposed circuit both active switches are turned on at ZVS. It assures high circuit efficiency and stability. PI control method is used in the proposed circuit.
result of inverter turn-on. Prior to the start of inverter operation the DC offset controller was operating, but effectively in open loop. Because of that, at the start of inverter operation, the PI controller’s output was saturated at the chosen limit which was set to about 0.5V. This limit represents the maximum available DC offset compensating current. There is good agreement between the measured response of figure 6.2 and the theoretical response shown in figure 6.3 which is based on equations (6.7) and (6.8). The steady state value of the response is non-zero because a compensating signal is generated by the controller to cancel the DC offset observed on open loop. The settling time is of the order of 7 seconds. The fundamental reasons for this relatively slow response are the large values of τ p and τ f and the small value of loop gain K. The slow rate of response is not