A Novel Architecture for single Precision Floating Point Multiplier Based on Vedic mathematics Ch Nagapavani & P Koteswar Rao

To multiply 52-bit mantissa in Double precision Floating point and to reduce the count of partial products obtained in a multiplication process Wallace tree multiplier is used..

The design, synthesis and simulation of 32-bit single precision floating point adder/subtraction & multiplier have been achieved using Xilinx 14.5i ISE tool.

The concept of IEEE single precision floating Point Multiplier[1] was implemented efficiently by Mohamed Al-Ashrafy , Ashraf Salem and Wagdy Anis in “ An efficient

By taking my previous research paper as base paper implemented the low area single precision floating point multiplier in this review work by using Nikhilam Vedic Sutra for 24

Abstract —In this paper we describe an efficient implementation of an IEEE 754 single precision floating point multiplier using vedic mathematics .The purpose of using

In this paper, the concepts of High speed compressors are used for the implementation of a High speed single precision binary Floating point multiplier by using

In this paper, floating point multiplication for single precision numbers is developed by using Karatsuba algorithm with vedic multiplier with different existing like

In this paper, the concepts of High speed compressors are used for the implementation of a High speed single precision binary Floating point multiplier by using IEEE