carry look-ahead logic
Design and Analysis of 64 bit Multiplier using Carry Look Ahead Logic for Low Latency and Optimized Power Delay Product
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Performance Analysis of 64-Bit Carry Look Ahead Adder
5
EFFICIENT HIGH SPEED ADDERS FOR 4-BIT MICROPROCESSOR
5
Design and Implementation of Low Power Efficient 8 bit Carry Look Ahead Adder using Adiabatic Technique
6
Analysis of Carry Select Adder Using Zero Carry Look Ahead Adder
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DESIGNS OF CARRY LOOK AHEAD BCD SUBTRACTOR FOR REVERSIBLE LOGIC APPLICATIONS.
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Design of a Novel Reversible ALU using an Enhanced Carry Look-Ahead Adder
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Design and Comparative Analysis of Various Adders through Pipelining Techniques
9
Comparative Study of Implementation of 8 Bit Carry Select Adder using Different Technologies
6
Design and FFT Analysis of Carry Look Ahead Adder
8
High Speed Time Efficient Reversible ALU Based Logic Gate Structure on Vertex Family
5
ASIC Design of Reversible Adder and Multiplier
5
CMOS Implementation of Low Power High Performance Fast Fourier Transform Using 180nm Technology
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5TClocked Carry Look Ahead Adder Design Using MIFG
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A Review in Designing of Adders Using Submicron Technology
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Implementation of Low Power 32 Bit Carry Look Ahead Adder using Adiabatic Logic
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Implementation of a Low Power Carry Look Ahead Adder Using Adiabetic Logic
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COMPARISON OF 32-BIT RIPPLE CARRY ADDER AND CARRY LOOK-AHEAD ADDER IN VHDL
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SURVEY ON INFORMATION EXTRACTION FROM CHEMICAL COMPOUND LITERATURES: TECHNIQUES AND CHALLENGES
10
Performance of Delay, Power and Area for Parallel Prefix Adders with Xilinx
7