dual threshold voltage technique
Dual Threshold Voltage Design for Low Power VLSI Circuits Sampangi Venkata Suresh
5
Power optimized variation aware dual-threshold SRAM cell design technique
9
Monotonic transition based forward body bias for dual threshold voltage low power embedded processors
5
Exploiting Read/Write Asymmetry to Achieve Opportunistic SRAM Voltage Switching in Dual-Supply Near-Threshold Processors
15
Implementation of Low Power Voltage Level Shifter using GALEOR Technique for Sub threshold Operation
5
A New Dual Threshold Technique for Leakage Reduction in 65nm Footerless Domino Circuits
7
A Survey on Dual-Threshold Technique for Leakage Reduction in 65nm Footerless Domino Circuits
7
A Novel High Performance Dual Threshold Voltage Domino Logic Employing Stacked Transistors
6
Analysis of Leakage Current Reduction Techniques in SRAM Cell in 90nm CMOS Technology
5
Index Terms: MTCMOS, FINFET, Schmitt trigger, power gating techniques, sleep transistor.
7
A Low Power 90nm Technology based CMOS Digital Gates with Dual Threshold Transistor Stacking Technique
5
Hybrid Domino XOR Gate with Dual Threshold Voltage Transistors
11
Investigation of threshold voltage and transconductance variations in PMOS
5
Data reliability and error correction for NAND Flash Memory System
157
Exploiting Read/Write Asymmetry to Achieve Opportunistic SRAM Voltage Switching in Dual-Supply Near-Threshold Processors
16
A REVIEW OF LOW POWER FLASH ADC USING THRESHOLD INVERTER QUANTIZATION TECHNIQUE
11
Complementary Pass Transistor Control Unit Design for Subthreshold Current Management in Digital Portable Systems
6
Cryogenic characterization of commercial SiC Power MOSFETs
5
Basic Analog and Digital Student Guide
174
Islanding Detection and Controlled Islanding in Emerging Power Systems Key Issues and Challenges
15