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gate oxide leakage current

A Survey on Dual-Threshold Technique for Leakage Reduction in 65nm Footerless Domino Circuits

A Survey on Dual-Threshold Technique for Leakage Reduction in 65nm Footerless Domino Circuits

... microprocessors. Leakage current of footerless domino circuit is analyzed by considering standby mode, clock is gated high ...and gate oxide leakage current with low dynamic node ...

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Aluminium oxide prepared by UV/ozone exposure for low-voltage organic thin-film transistors

Aluminium oxide prepared by UV/ozone exposure for low-voltage organic thin-film transistors

... the gate-source leakage current by a factor of 10 as a function of aluminium oxide ...bi-layer gate dielectrics vary between 5 and 12 V and the electrical breakdown field is at least 5 ...

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Computationally efficient quantum mechanical technique to calculate direct tunnelling gate leakage current in metal oxide semiconductor structures

Computationally efficient quantum mechanical technique to calculate direct tunnelling gate leakage current in metal oxide semiconductor structures

... 兲 gate current in metal-oxide-semiconductor 共 MOS 兲 ...the gate-dielectric layer even in the sub-1-nm-thickness regime, we have simplified the determination of ⌫ in devices where it is too ...

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Failure analysis using IDD current leakage and photo localization for gate oxide defect of CMOS VLSI

Failure analysis using IDD current leakage and photo localization for gate oxide defect of CMOS VLSI

... the current technology due to metal interconnection layers and dense for front side failure analysis ...DD current of the faulty logic cells during the transition ...

5

The consequence of Source/Drain factor 
		toward drive current in 10nm SOI MOSFET device

The consequence of Source/Drain factor toward drive current in 10nm SOI MOSFET device

... the gate length and gate oxide, scalling the gate oxide will lead to enchances the drive current and low short channel effect (SCE) but when we scale down this device the SCE ...

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Designing a Full Adder Circuit Based on  Quasi Floating Gate

Designing a Full Adder Circuit Based on Quasi Floating Gate

... floating gate transistor within the parallel re- sistors combining with gate capacitor involves the maximum power dissipation comparing to other ...the gate oxide thickness and increase of ...

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To Reduce the Leakage Power of CMOS Logic Circuit through Lactor Technique

To Reduce the Leakage Power of CMOS Logic Circuit through Lactor Technique

... reduce leakage power in efficient way but the main disadvantage of each technology that limits the application of each ...charge leakage, and power ...for current and future ...Sub-threshold ...

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DESIGN AND PARAMETRIC ANALYSIS OF DUAL WORK FUNCTION PILE GATE APPROACH FOR LOW LEAKAGE FINFET

DESIGN AND PARAMETRIC ANALYSIS OF DUAL WORK FUNCTION PILE GATE APPROACH FOR LOW LEAKAGE FINFET

... the leakage current in the standard bulk ...and oxide confinement are all having a few pros and ...Pile gate FinFET structure is introduced to overcome the short channel effects, unlike from ...

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Analysis of Leakage Current Reduction Techniques in SRAM Cell in 90nm CMOS Technology

Analysis of Leakage Current Reduction Techniques in SRAM Cell in 90nm CMOS Technology

... on leakage current minimization in single static random access memory (SRAM) cell in 90nm complementary metal oxide semiconductor (CMOS) ...The leakage current mainly consists of sub ...

5

Low series resistance structures for gate dielectrics with a high leakage current

Low series resistance structures for gate dielectrics with a high leakage current

... gion and small groundplanes show the most unambiguous and promising RF C-V measurement results. The influence of larger groundplanes decreases the precision with which the intrinsic capacitance value in accumulation can ...

107

Heavy-ion-induced breakdown in ultra-thin gate oxides and high- k dielectrics

Heavy-ion-induced breakdown in ultra-thin gate oxides and high- k dielectrics

... threshold oxide field for the onset of enhanced radiation-induced leakage current or ...in leakage current for each subsequent ion shot and at each irradiation voltage step clearly ...

9

Impact of Fin Dimensions on Performance of Adder and Subtractor

Impact of Fin Dimensions on Performance of Adder and Subtractor

... the current through the device increases For high layout density, the ratio between fin height and the achievable pitch between to successive fins has to be ...drive current per silicon area as per planar ...

8

Long-term reliability degradation of ultrathin dielectric films due to heavy-ion irradiation

Long-term reliability degradation of ultrathin dielectric films due to heavy-ion irradiation

... enhanced leakage current and/or premature oxide breakdown than lower-LET ...the gate leakage current in the following ...

6

Effects of Energy Relaxation via Quantum Coupling Among Three Dimensional Motion on the Tunneling Current of Graphene Field Effect Transistors

Effects of Energy Relaxation via Quantum Coupling Among Three Dimensional Motion on the Tunneling Current of Graphene Field Effect Transistors

... ing current and quantization of the inversion layer when the channel electron velocity is higher than the thermal velocity [10, ...the gate leakage current [10, ...tunneling current ...

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Title: Study of Outpouring Power Diminution Technique in CMOS Circuits

Title: Study of Outpouring Power Diminution Technique in CMOS Circuits

... on gate length and oxide ...sub-threshold leakage current, thereby increase in the static power ...of leakage current in a MOS transistor are shown in Figure ...the ...

7

Simulation, fabrication and characterization of NMOS transistor

Simulation, fabrication and characterization of NMOS transistor

... Threshold Voltage and Leakage Current, with different channel length and oxide gate for the Long Channel NMOS transistor too has been investigated.. The data from the experiment conducte[r] ...

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Analysis of AlGaN/GaN high electron mobility transistors with nonalloyed Ohmic contacts achieved by selective area growth using plasma assisted molecular beam epitaxy

Analysis of AlGaN/GaN high electron mobility transistors with nonalloyed Ohmic contacts achieved by selective area growth using plasma assisted molecular beam epitaxy

... 1 V), indicating that Ohmic contact was not achieved in this sample due to the energy barrier at the interface between the nonalloyed metals and GaN epilayer. The regrown GaN layer by PAMBE can effectively narrow the ...

6

High temperature pulsed gate robustness testing of SiC power MOSFETs

High temperature pulsed gate robustness testing of SiC power MOSFETs

... any current conduction through the DUTs. Current conduction is undesirable as it would not only lead to unnecessarily heat up of devices, but could also have an impact on the monitored ...

6

Silicon heterojunction metal wrap through solar cells – a 3D TCAD simulation study

Silicon heterojunction metal wrap through solar cells – a 3D TCAD simulation study

... This study assumes a non-conformal growth of the a-Si:H emitter, which does not electrically insulate the via surface in SHJ-MWT solar cells. To confirm this assumption, a 550 nm thick layer of a-Si:H was deposited on a ...

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High Speed Noise Tolerant Domino Circuit For Wide Fan in AND OR Gates

High Speed Noise Tolerant Domino Circuit For Wide Fan in AND OR Gates

... OR gate is shown. When Power is zero, the current is also ...the current in the circuit is also increases. The current is in negative because PMOS is operate in reverse biased ...negative ...

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