IEEE-754
IEEE 754, VDM
6
Combining Secret Sharing and Garbled Circuits for Efficient Private IEEE 754 Floating-Point Computations
20
Survey of Matrix Multiplication using IEEE 754 Floating Point for Digital Image Compression
8
Design and Analysis of Matrix Multiplication using IEEE 754 Floating Point Multiplier Partition Technique
8
Review on 32 bit single precision Floating point unit (FPU) Based on IEEE 754 Standard using VHDL
6
Trans-Floating-Point Arithmetic Removes Nine Quadrillion Redundancies From 64-bit IEEE 754 Floating-Point Arithmetic
6
Double Security Watermarking Algorithm for 3D Model using IEEE 754 Floating Point Arithmetic
5
IEEE 754 compliant floating point fused add sub unit
5
Design and Implementation of IEEE 754 Addition and Subtraction for Floating Point Arithmetic Logic Unit
7
High Speed IEEE 754 Floating Point Multiplier using Different Types of Adder
6
Resilient Iterative Linear Solvers Running Through Errors.
169
FPGA Implementation of Low-Area Floating Point Multiplier Using Vedic Mathematics
5
An Efficient Implementation of Double Precision Floating Point Multiplier Using Booth Algorithm
6
VLSI Implementation of Neural Network
10
FPGA based High Speed Double Precision Floating Point Divider
6
Implementation of 32 bit Floating Point Multiplier and Adder for FFT Processor Using VHDL
6
FPGA based Implementation of High Speed Double Precision Floating Point Multiplier with Tiling Technique using Verilog
9
Design and Implementation of low power Floating Point Multiplier
9
Implementation Of A High Speed Binary Floating Point Multiplier Using Dadda Algorithm In Fpga
7
Design and Implementation of Floating Point Complex number Multiplier Using Modified Vedic Algorithm
5