low power CMOS digital circuits
Ultra-Low Power Design of Digital CMOS Logic Circuits
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Efficient Power Utilization in High Frequency CMOS Digital Circuits using MTCMOS Technology
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AVTS Approach To Digital CMOS Circuits For Diminishing Complete Power Expenditure
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Design of Low Power Energy Efficient CMOS Circuits with Adiabatic Logic
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Analysis of 16 bit carry look ahead adder A subthreshold leakage power perspective
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Design Of Low Power Cmos Adder, Serf, Modified Serf Adder
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Analysis of GDI Technique for Digital Circuit Design
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Low Power Design Techniques in CMOS Circuits : A Review
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Leakage Power Reduction in CMOS VLSI Circuits
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Comparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits
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Minimization Leakage Current of Full Adder Using Deep Sub-Micron CMOS Technique
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Performance analysis on various low power CMOS digital design techniques
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A Novel Design of Hybrid 2 Bit Magnitude Comparator
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Ultra Low Power Designing for CMOS Sequential Circuits
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ABSTRACT : Adiabatic array logic allows designing low power digital circuits with more power saving despite having
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THE DESIGN OF HIGH PERFORMANCE THREE INPUT XOR GATE BASED ON COMPOUND GATE METHODOLOGY
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Performance Analysis of CMOS and GDI Comparators
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Design and Comparative Analysis of EEAL Sequential Circuit for Low Power VLSI Application
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Reduced Comparator Flash ADC for ECG Applications
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Capacitance Measurement Methods for Integrated Sensor Applications
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