on-chip power dissipation
Online Testable Reversible Circuits using reversible gate
... Abstract - Reversible logic is very promising due to its low power consumption. As the advancement of nanometer technology transient fault occur during the operation of circuit. Traditional technique such as ...
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Vol 1, No 3 (2013)
... Earlier power consumption was of secondary concern. In nanometre technology power has become the important issue because increasing transistor count, higher speed of operation, greater leakage ...currents. ...
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Process Development for an Ultra High Density Chip-on-Chip Power Module.
... Flex circuits are ordered from American Circuit, Inc. Materials of Part A are depicted in Figure 1-2 where each polyimide layer is 1mil (25.4μm) thick and each Cu layer is 1oz (35μm). The Parts B and C are single-layer ...
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Reducing Power Dissipation in SRAM during Test
... Reducing power dissipation during testing of complex Systems-on-Chip (SoC) has been acknowledged as a major ...the power dissipation during test mode can be several times larger than in ...
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Enhancement of heat dissipation in an electronic chip cooling system using graphite fins
... lower power consumption, more fundamental research is required to improve the cooling systems from material engineering point of view alongside redesigning the available cooling systems(Gupta et ...heat ...
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Reduction of Energy Consumption in Noc by Using Encoding Techniques
... the power dissipated links of a network on-chip (NoC - Network on Chip) which starts to compete with the power dissipated by the other elements of the communication subsystem like the routers ...
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Design of low power network on chip using data encoding techniques
... On Chip (SoC) design in designs incorporating large number of processing ...overall power dissipation is due to the interconnection ...dynamic power dissipation in a NoC ...the ...
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A Modified SRAM Based Low Power Memory Design
... hence, power consumption becomes a critical ...same chip along with the ...total power dissipation of the ...its power consumption has always been researched ...dynamic power ...
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A Novel Low Power Optimization for On-Chip Interconnection
... To overcome the above undesirable effects, many techniques developed over these years. Repeaters are often used [2] to minimize the delay required to propagate a signal through those interconnect lines that are best ...
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A Comprehensive Study on Power Reduction Techniques in Deep Submicron Technologies
... static power dissipation i.e. leakage power dissipation has become a challenging area for VLSI chip ...leakage power minimization techniques have been presented in this ...
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Energy Efficient SRAM
... their power consumption must be considered during the designing process of the ...the power consumed by the ...low power is crucial so as to replace ...delay, power consumption and stability ...
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Vol 8, No 6 (2018)
... Power dissipation has become a significant and more critical design parameter for VLSI circuits especially at deep sub- micron ...of power sources used and their ...at chip level has resulted ...
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Design & Analysis of Adiabatic Logic based Multiplexers for Ultra Low Power Applications
... communication, power dissipation has become one of the major design concerns along with chip area and device ...reduce power dissipation at various levels of design abstraction has ...
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Thermal Control Methods for Reducing Heat in 3D ICs - TSV (Through-Silicon-Via)
... Moore’s law describes the Long-term trend in the history of the integrated circuit technology in which the number of low-cost installable transistors on an integrated circuit has doubled roughly every two years. However ...
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A LOW POWER LEVEL SHIFTER USING POWER GATING TECHNIQUE FOR SOC APPLICATIONS
... The current flowing through the nodes NH and NL at the beginning of their high to low transition could be of concern [5]. Thus, to reduce this effect, two PMOS devices (P2 and P3) are adopted. P4 and P5 helped in ...
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Power dissipation of a superconducting radio frequent source at 6K
... holder to heat up so a little extra dissipation is not necessarily a prob- lem. Through the thermometer flows only a very low current that changes slightly as the temperature changes the resistance of the ...
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A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band
... based NoC architectures are not scalable in terms of performance and energy consumption. Folded architectures such as Torus and Folded Torus were proposed to improve the performance of Mesh based NoCs while retaining the ...
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Energy Efficient Novel Design of Static Random Access Memory Memory Cell in Quantum-dot Cellular Automata Approach
... and power consumption is compared with the reported ...overall power up to 35.3% at maximum energy dissipation of circuit, ...energy dissipation of circuit, 36.1% at minimum energy ...
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Impact of on-chip inductance on power supply integrity
... SoC power distribution grid is ...for power delivery due to I/O and ESD ...on-chip power grid is connected to the package with regu- lar bump connections, as depicted in fig ...for ...
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Towards Low-Power On-chip Auditory Processing
... For the analog approach, we use a 32-channel bandpass filter bank with exponentially spaced corner frequencies for the frequency decomposition. The frequency decomposition is followed by a peak detector circuit and a log ...
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