system-on-a-chip architectures
Ultralarge-Scale System-on-Chip Architectures using Scan Test Bandwidth Management
... This paper shows a few systems utilized to determine issues surfacing while applying check transmission capacity administration to substantial modern multicore framework on-chip (SoC) plans with installed test ...
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Quality-of-service and error control techniques for mesh-based network-on-chip architectures
... proposed system-level performance and power models for a shared-memory internet protocol/asynchronous transfer mode switching ...proposed system-level models for the same. Pamunuwa et al. [36] performed a ...
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Application driven evaluation of network on chip architectures for parallel signal processing
... parallel architectures. We present a network-on-chip approach to derive an optimal communication architecture for a parallel Turbo-Decoder ...a system significantly de- pends on the efficiency of the ...
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Multicast-Aware High-Performance with Encript Wireless Network-On-Chip Architectures
... a system size of 64 cores, the SW-based networks achieve highest throughput with lowest energy dissipation when the maximum port count in a router is restricted to ...whole system is divided into multiple ...
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A Review of System-On-Chip Bus Protocols
... multilayer architectures, the bandwidth can be improved when maximum transactions occur in the same bus level or the same bus ...bus-based architectures are also not suitableto the battery-driven portable ...
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Comparative Analysis of Different Topologies Based On Network-on-Chip Architectures
... Recent technological development in the field of integrated circuits has enabled designers to accommodate billions of transistors. The level of integration has enhanced computational power enormously. The exponential ...
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Design and Optimization of System-on-chip (SOC)
... transistors chip, it may not be possible to send a global signal across the chip within real-time ...interconnection architectures may prevent these systems to meet the performance required by many ...
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Reliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures (RESEARCH NOTE)
... Nowadays, faults and failures are increasing especially in complex systems such as Network-on-Chip (NoC) based Systems-on-a-Chip (SoC) due to the increasing susceptibility and decreasing feature sizes. On ...
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Bridging the Gap between Software and Hardware Designers Using High-Level Synthesis
... the system energy consumption (power ...memory architectures [17], but they are usually limited in terms of capac- ...memory architectures, but there is no clear winning yet and systems will combine, ...
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A System on a Chip Design of the AES Cryptographic System
... high-speed architectures, designers can decide to use the loop-unrolled architecture as the basic structure, while the rolled (basic iterative) architecture is used when a low area design is ...
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Elliptic-curve cryptographic architectures for system-on-chip based on field programmable gate arrays
... hardware system based on Nios II 32-bit RISC embedded processor as the prototyping ...development system contains a powerful and flexible IDE, the Quartus II SOPC Builder that facilitates the tasks of ...
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On-chip Interconnection Network for Accelerator-Rich Architectures
... a system grows, the amount of dedicated buffer space de- voted to these accelerators grows as ...of chip resources, previous work provides a mechanism to allocate these buffers in cache space [11, 9, ...
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A Study on Network-On-Chip architecture using Genetic Algorithm
... silicon chip. Figure1 shows a simple NoC system, designed by processing elements and ...on chip (NoC) has emerged as the design paradigm for design of scalable on-chip communication ...
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SAP with Oracle on UNIX and NFS and NetApp Storage
... Corporations today require their SAP applications to be available 24 hours a day, seven days a week. Consistent levels of performance are expected, regardless of increasing data volumes and routine maintenance tasks such ...
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Design of an AC Servo Controller for a Dynamic Simulation Test System for Hydraulic Excavators Based on a System-on-chip Architecture
... test system for a hydraulic excavator, which is a closed loop system whose core is the AC servo ...test system of the hyd- raulic excavator to produce the corresponding ...
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Smart Grid. System of Systems Architectures
... The silo architecture, though adequate in the past, will be inefficient in the future for several reasons. One reason is increasing demand by a number of stakeholders for greater c[r] ...
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Using single CCD and CMOS image sensor to construction video and image acquisition system
... mission system requirement, laid the foundation for the further study of synchronous motion system of dual CCD camera ...conversion chip MAX3243 to realize the conversion between CMOS logic level and ...
7
ON-CHIP PERMUTATION NETWORK IN MULTIPROCESSOR SYSTEM ON-CHIP FOR ADDRESSING PERMANENT ERRORS
... The ILT method routes data sequentially from each pair of adjacent wires to a set of available spare wires, allowing each pair to be tested for intermittent and permanent faults. This is achieved without interrupting ...
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Adaptive digital signal processing Java teaching tool
... This paper has reviewed adaptive signal processing architectures and applications, and provided a short PDF tutorial on adaptive DSP. We have provided links to the adaptive DSP applet contained on this IEEE ...
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OpenCL Programming for the CUDA Architecture. Version 2.3
... To achieve high arithmetic throughput, applications need high memory throughput as well. For this reason, GPUs offer higher memory bandwidth than CPUs – typically an order of magnitude higher – and several specialized ...
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