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systems-on-a-chip design

DESIGN CHALLENGES IN MULTIPROCESSOR SYSTEMS-ON-CHIP

DESIGN CHALLENGES IN MULTIPROCESSOR SYSTEMS-ON-CHIP

... Hardware/software partitioning builds a custom heterogeneous system with a CPU and a hardwired accelerator, based on program characteristics and performance requirements. A variety of hardware/software partitioning ...

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Deploying a Telecommunication Application on Multiprocessor Systems-on-Chip

Deploying a Telecommunication Application on Multiprocessor Systems-on-Chip

... The particular form of the task graph of many telecom- munication applications permits a high level of coarse grained parallelism. We consider a classification appli- cation on a telecommunication oriented ...

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Organs on a Chip: A Future of Rational Drug Design

Organs on a Chip: A Future of Rational Drug Design

... -like systems, and help advance the potential of stem cell therapies and regenerative medicine [18] ...microfluidic systems and through ability of microfluidics to control stem cell microenvironments with ...

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A Study on Network-On-Chip architecture using Genetic Algorithm

A Study on Network-On-Chip architecture using Genetic Algorithm

... VLSI systems implemented on a single silicon ...VLSI design methodology. Network on chip (NoC) has emerged as the design paradigm for design of scalable on-chip communication ...

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A System on a Chip Design of the AES Cryptographic System

A System on a Chip Design of the AES Cryptographic System

... to design strong encryption techniques to protect private ...many systems such as smart cards, mobile phones, USB keys and banking systems ...

8

Reliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures (RESEARCH NOTE)

Reliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures (RESEARCH NOTE)

... It is worth mentioning that the reliability assessment is a key method for dependability evaluation which can be used to make decisions in the design of reliable systems [5]. The reliability assessment can ...

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A fault observant real-time embedded design for network-on-chip control systems

A fault observant real-time embedded design for network-on-chip control systems

... For example, the automotive industry has used temperature- hardened processors for control tasks around the engine block while space missions use radiation-hardened processors to avoid damage from solar radiation. An ...

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Communication-centric debug of systems-on-chip using networks-on-chip

Communication-centric debug of systems-on-chip using networks-on-chip

... ing design complexity which results in a design productivity gap between the chip complex- ity growth (doubling every 18 months) and the productivity growth (doubling roughly every 4 years), see ...

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Using System-on-a-Programmable-Chip Technology to Design Embedded Systems

Using System-on-a-Programmable-Chip Technology to Design Embedded Systems

... Two new SoPC development boards from Altera and Xilinx can be seen in Figures 5 and 6. These boards both support a wide array of I/O hardware interfaces including VGA, audio, PS/2, USB, Ethernet, serial I/O, parallel ...

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Design of Network on Chip with an Arbiter

Design of Network on Chip with an Arbiter

... a design with approximately one billion transistors on a single ...multiprocessor systems-on-chip (MPSoC) [1] to meet the current requirements of real time ...

7

System-on-Chip Design and Implementation

System-on-Chip Design and Implementation

... The design of a modern System-on-Chip (SoC) is a complex task involving a range of skills and a deep understanding of a hierarchy of perspectives on design, from processor architecture down to signal ...

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A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band

A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band

... and chip area ...memory systems in order to provide fast and efficient means for data access and sharing between ...a chip increases, the performance is limited by the communication among and within ...

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Designing Systems-on-Chip Using Cores

Designing Systems-on-Chip Using Cores

... top-level design, which can then be simulated, synthesized, floorplanned and used for early software ...the design which may not be caught until much later in the ...top-level design is the main ...

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Design and Optimization of System-on-chip (SOC)

Design and Optimization of System-on-chip (SOC)

... the chip, and has spurred the Non-Uniform Cache Architecture (NUCA) concept as in ...the chip area and power budgets in distributed, communication-centric systems are progressively being dominated by ...

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Virtual Platforms in System-on-Chip Design

Virtual Platforms in System-on-Chip Design

... embedded systems, virtual platforms solve one of today’s biggest challenges in these systems: software development, debug and validation before the hardware board is available, enabling concurrent ...

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Extending Platform-Based Design to Network on Chip Systems

Extending Platform-Based Design to Network on Chip Systems

... based systems have to meet a variety of requirements, including correct functionality, sufficient throughput, latency and memory, high energy efficiency, maintainability and fault ...

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FRONT-END DESIGN FLOWS FOR SYSTEMS ON CHIP: AN EMBEDDED TUTORIAL

FRONT-END DESIGN FLOWS FOR SYSTEMS ON CHIP: AN EMBEDDED TUTORIAL

... the design of an integrated circuit or a systems is called Design ...A design flow defines not only the steps to be followed, but also the software tools required to carry out those ...the ...

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Design Partitioning Methodology for Systems on Programmable Chip

Design Partitioning Methodology for Systems on Programmable Chip

... actual systems for multimedia services have demanding applications that can be driven by portability, performance, cost, consumption and ...the design of portable multimedia systems is to find a good ...

6

Design of Networks-on-Chip for Real-Time Multi-Processor Systems-on-Chip

Design of Networks-on-Chip for Real-Time Multi-Processor Systems-on-Chip

... router design [9] supports both GS and BE traffic and the slot tables, controlling the switching of the GS-traffic through the routers, are implemented inside the ...

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An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links

An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links

... the conventional wired interconnects remain a bottleneck of NoC. Long range high- bandwidth on-chip wireless data links are proposed as an energy efficient alternative [18] where the multihop wired paths between ...

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