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Threshold logic

DESIGNING FULL ADDER USING n-NOR BASED THRESHOLD LOGIC GATES

DESIGNING FULL ADDER USING n-NOR BASED THRESHOLD LOGIC GATES

... differential threshold logic flip- flop called ...a threshold function of its ...their logic comes with n-NOR cells is ...conventional logic cells and n-NORs, is shown to have ...

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LOW POWER ENERGY EFFICIENT FILPFLOP   DESIGN USING THRESHOLD LOGIC

LOW POWER ENERGY EFFICIENT FILPFLOP DESIGN USING THRESHOLD LOGIC

... differential threshold logic flipflop called ...a threshold function of its ...their logic cones with PNAND cells is ...conventional logic cells and PNANDs, is shown to have ...

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Delay Analysis for Current Mode Threshold Logic Gate Designs

Delay Analysis for Current Mode Threshold Logic Gate Designs

... mode logic (DCCML), which results in both speed and switching energy [power-delay product (PDP)] improvements over the approaches in [1] and ...any threshold logic ...

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Design of threshold logic gate using Testing Delay in Current Mode

Design of threshold logic gate using Testing Delay in Current Mode

... An automatic test pattern generation approach to detect delay defects in a circuit consisting of current mode threshold logic gates is introduced. Each generated pattern should excite the maximum ...

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Application of Single Electron Threshold Logic based Device: - A case study

Application of Single Electron Threshold Logic based Device: - A case study

... The design and simulation of control unit of a process controller using Single Electron Threshold Logic Gate is presented. The complete circuit to implement the control unit has been designed and verified ...

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LOW POWER THRESHOLD LOGIC DESIGNING APPROACH FOR HIGH ENERGY EFFICIENT FLIP-FLOP

LOW POWER THRESHOLD LOGIC DESIGNING APPROACH FOR HIGH ENERGY EFFICIENT FLIP-FLOP

... using threshold logic have been incorporated into modern design ...include logic synthesis and restructuring to reduce switching activity, gate sizing, technology mapping, retiming, voltage scaling, ...

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Design of Threshold Logic Flip Flops for Achieving Efficient Performance of System
K Lakshmi Narayana & B Satyasai

Design of Threshold Logic Flip Flops for Achieving Efficient Performance of System K Lakshmi Narayana & B Satyasai

... to threshold gates due to the presence of the latch-based ...of threshold flip-flops includes new retiming algorithms, the design of asynchronous circuits, threshold logic-based ...

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Efficient minimization Techniques for threshold Logic Gate

Efficient minimization Techniques for threshold Logic Gate

... multi threshold logic [18] and MOBILE where MOBILE is monostable bistable logic ...and threshold logic and simulate it using ...

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Sub-Threshold Logic and Standard Cell Library

Sub-Threshold Logic and Standard Cell Library

... Abstract: This paper presents the sub-threshold logic and standard cell library for it. Standard cell library consists of basic gates as well as universal gates (INVERTER, EX-OR, NAND, NOR gate) in ...

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Design of Single Ended 8T SRAM Cell using Sub threshold Logic

Design of Single Ended 8T SRAM Cell using Sub threshold Logic

... The threshold voltage variations in the transistor and increased power dissipation increases with number of transistors which in turns affects the read and write stability of the ...

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A statistical reliability model for single-electron threshold logic.

A statistical reliability model for single-electron threshold logic.

... SET-based logic gates by presenting a statistical model which takes into account the process variations (especially random background charges) and input ...NAND logic gates are discussed in this ...

100

A Novel High-Speed and Low-Energy 1-Bit Full Adder Cell Based on CNFET Technology

A Novel High-Speed and Low-Energy 1-Bit Full Adder Cell Based on CNFET Technology

... Capacitive Threshold Logic (CTL) and Transmission Gate Logic (TGL), a novel Full Adder cell based on 32nm Carbon Nanotube Field Effect Transistors (CNFETs) is presented in this ...

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DESIGN OF PD AND HIGH PERFORMANCE VCO FOR PLL WITH 45 nm CMOS TECHNOLOGY

DESIGN OF PD AND HIGH PERFORMANCE VCO FOR PLL WITH 45 nm CMOS TECHNOLOGY

... 2. K.Rajasekhar, S.Adilakshmi, T.B.K. Manoj kumar ,”Design of High Performance Phase Locked loop for Multiple outputs with Ultra Low Power Sub Threshold Logic”, International Journal of Engineering Research ...

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Design of low power 16x16 SRAM Array using GDI logic with dynamic threshold technique

Design of low power 16x16 SRAM Array using GDI logic with dynamic threshold technique

... low logic complexity design low power consumption achieved ...Dynamic Threshold logic. The technique behind the dynamic threshold MOS is that the input voltage Vbs is greater than Zero for ...

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An Efficient Ultra Low Power Circuit by Using Subthreshold Adiabatic Logic

An Efficient Ultra Low Power Circuit by Using Subthreshold Adiabatic Logic

... sub threshold logic, circuits operated with the power clock Vdd, below than the threshold voltage (Vth) of the transistor, and it employ the sub threshold leakage current as a guiding ...CMOS ...

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Image Segmentation based on FUZZY GLSC Histogram with Dynamic Similarity Discrimination Factor

Image Segmentation based on FUZZY GLSC Histogram with Dynamic Similarity Discrimination Factor

... Image threshold is a simple and popular technique for image segmentation used in image processing applications to separate foreground or background of an ...the threshold in bimodal histogram images because ...

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Design of Low Power Full Adder Using ONOFIC Approach

Design of Low Power Full Adder Using ONOFIC Approach

... Abstract: Improving performance with reduced power consumption and chip area are the main constraint for designing VLSI CMOS circuits. The high performance low power ONOFIC approach for VLSI CMOS circuits reduces the ...

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An Intelligent Fuzzy Based Energy Detection Approach for Cooperative Spectrum Sensing

An Intelligent Fuzzy Based Energy Detection Approach for Cooperative Spectrum Sensing

... Cognitive radio systems are helpful to access the unused spectrum using the popular technique, referred to as spectrum sensing. Spectrum sensing involves the detection of primary user (PU) signal using dynamic spectrum ...

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A Centralized Energy Coordinator Reliant on BESS and DER PV Operation

A Centralized Energy Coordinator Reliant on BESS and DER PV Operation

... internal logic of Controller “A” is presented in Figure ...the logic, setting the A1 and A2 variables (shown in green) to either a positive, negative, or null value directly impact the magnitude of either a ...

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Fault Detection in Hydraulic System Using Fuzzy Logic

Fault Detection in Hydraulic System Using Fuzzy Logic

... fuzzy logic over conventional method like Wald’s sequential test [4] has several ...Fuzzy logic is a good option because there is no general mathematical model available which describes the output fault ...

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