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very-high-speed signal processing

Design of Power Efficient Rounding-Based Accurate Multiplier for High-Speed Digital Signal Processing In Xilinx

Design of Power Efficient Rounding-Based Accurate Multiplier for High-Speed Digital Signal Processing In Xilinx

... for High-Speed yet Energy EnergyEfficient Digital Signal Processing” IEEE transactions on very large scale integration (VLSI) systems ...

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Comparative Analysis and Efficient VLSI Implementation of FIR Filter

Comparative Analysis and Efficient VLSI Implementation of FIR Filter

... digital signal processing within an FPGA is the ability to adapt the implementation to match system requirements [2, ...or high-speed system, you can take advantage of the parallelism within ...

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DESIGN OF 64-BIT ALU USING VEDIC MATHEMATICS FOR HIGH SPEED SIGNAL PROCESSING RELEVANCE’S

DESIGN OF 64-BIT ALU USING VEDIC MATHEMATICS FOR HIGH SPEED SIGNAL PROCESSING RELEVANCE’S

... The Proposed ALU consist of logical and unit and arithmetic units. The logical operators and arithmetic operators are connected to the Multiplexer. They possess same inputs and produces output based on the selection line ...

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Signal generation and processing in high-frequency / high-speed silicon-based integrated circuits

Signal generation and processing in high-frequency / high-speed silicon-based integrated circuits

... large signal mode. Since it is very difficult to accurately predict the oscillation amplitude, especially at RF frequencies due to inadequate and inaccurate modeling, it is extremely difficult to achieve ...

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Direct RF Sampling GNSS Receiver Design and Jitter Analysis

Direct RF Sampling GNSS Receiver Design and Jitter Analysis

... This high sampling frequency represents an important challenge for the DRFS front-end design since both the ADC and the digital signal processing that follows need to cope with very ...

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Design and Implementation of 8X8 Truncated Multiplier on FPGA

Design and Implementation of 8X8 Truncated Multiplier on FPGA

... digital signal processing. Parallel multipliers provide a high-speed method for multiplication, but require large area for VLSI ...most signal processing applications, a rounded ...

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High speed and Area Efficient Rounding Based Approximate Multiplier for Digital Signal Processing

High speed and Area Efficient Rounding Based Approximate Multiplier for Digital Signal Processing

... is very low when case one and four are considered when compared with other two ...the speed and reduce the power consumption, the sign detector and sign set blocks are omitted from the architecture, ...

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Signal Processing in High-Speed Optical Communications and Impact on Electronic Subsystems

Signal Processing in High-Speed Optical Communications and Impact on Electronic Subsystems

... a very narrow linewidth laser is required at the transmitter and receiver because of the sensitivity of OFDM to frequency offset and phase noise ...data signal, with a bandwidth equal to the signal ...

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VLSI design of high-speed adders for digital signal processing applications.

VLSI design of high-speed adders for digital signal processing applications.

... Figure 4.4 shows the schematic of a novel 6—transistor transmission gate Ex c lu s !ve-OR gate C3 0] . The same logic function when realised in conventional static CMOS requires 14 devices. Transmission gates can be used ...

180

Optimization of Multirate Polyphase Decimator
          using MCM and Digit Serial Architecture

Optimization of Multirate Polyphase Decimator using MCM and Digit Serial Architecture

... whereas speed of the system by using ...and speed for ...digital signal processing system which requires very less power dissipation and maintaining higher ...power, high ...

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Cosine-Modulated Multitone for Very-High-Speed Digital Subscriber Lines

Cosine-Modulated Multitone for Very-High-Speed Digital Subscriber Lines

... the very high level of RFI still result in interference which de- grades the performance of z-DMT ...or very small variation in amplitude over each data block of DMT ...

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Conservative Slow Start: Controlling Losses in Very High Speed Networks

Conservative Slow Start: Controlling Losses in Very High Speed Networks

... the injection of packets into the network according to some in- dication of the session available bandwidth [5], [9]. However, this approach comes with a cost to the kernel, with additional timers to manage. Another ...

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Parallel Processing Technique for High Speed Object Recognition

Parallel Processing Technique for High Speed Object Recognition

... is very easy to ...image processing application for parallel ...be high for the input in a range and its output will be low for the input outside the ...

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Signal Integrity Analysis of High Speed Interconnects in SATA Connector

Signal Integrity Analysis of High Speed Interconnects in SATA Connector

... ---------------------------------------------------------------------***---------------------------------------------------------------------- Abstract - In this upcoming high speed digital interconnecting ...

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Cataract Detection

Cataract Detection

... of high speed ...for high speed processing is increasing as a result of expanding computer and signal processing ...time signal and operations are significant to ...

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Detection of natural crack in wind turbine gearbox

Detection of natural crack in wind turbine gearbox

... by processing for fault diagnosis of rotating machinery with multiple bearings, such as wind turbine gearbox, can be a challenging task, as data are usually required in three perpendicular directions for a ...

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Over-the-air demonstration of spatial multiplexing at high data rates using real-time base-band processing

Over-the-air demonstration of spatial multiplexing at high data rates using real-time base-band processing

... In particular, the JT separates the data streams in advance so that each user receives only the desired signal, while the signals of all other users are forced to zero. But this forc- ing of zeros is costly in ...

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Parallel and distributed processing in high speed traffic monitoring

Parallel and distributed processing in high speed traffic monitoring

... in processing the entire stream of incoming packets ...most processing takes place on the card and only statistics are sent to the host, or when the host accesses packets ir- regularly and only for checking ...

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Piggyback Scheme over TCP in Very High Speed Wireless LANs: Review

Piggyback Scheme over TCP in Very High Speed Wireless LANs: Review

... to high error recovery delays, especially over high delay ...over high delay paths, because the SACK option cannot speed up individual ...

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White Paper: Video Compression for CCTV

White Paper: Video Compression for CCTV

... Like JPEG, the wavelet method was also developed for coding individual frames. In the JPEG method, the image is first divided up into 8x8 blocks that are then coded individually. But the wavelet method also includes ...

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