[PDF] Top 20 An Efficient Flexible Architecture for Error Tolerant Applications
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An Efficient Flexible Architecture for Error Tolerant Applications
... [13] applications usually requires more time for execution of these operations, the reconfigurable architecture is a way out for ...single flexible architecture differentiates from other ... See full document
7
An Efficient VLSI-EDDR Architecture for Motion Estimation in Testing Applications
... introduce design for testability (DFT). DFT focuses on increasing the ease of device testing, thus guaranteeing high reliability of a system. DFT methods rely on reconfiguration of a circuit under test (CUT) to improve ... See full document
5
Flexible and an Efficient Hardware Architecture for A Secured Data Communication
... Security processing is computation intensive, which normally includes lookup and fetching/updating of parameters (keys, encryption/authentication algorithms, initial values, and security-related protocol information), ... See full document
7
Distributed Proximal Gradient Algorithm for Partially Asynchronous Computer Clusters
... an error-tolerant, communication efficient, yet versatile distributed algorithm has become vital for the success of many large-scale machine learning ...the flexible proximal gradient ... See full document
32
An Area Efficient Architecture For Error Correction Codes And Parsavel Checks
... Detecting and correcting errors like important reliability are troublesome in signal process that will increase the utilization of fault tolerant implementation. In modern signal process circuits, it's common to ... See full document
9
Efficient Data Access in Disruption Tolerant Networks with Drama Architecture
... A common technique used to improve data access performance is caching, i.e., to cache data at appropriate network locations based on query history, so that queries in the future can be responded with less delay. Although ... See full document
6
An Efficient Error Tolerant Adder Using Gate Diffusion Technique with Low power-high Speed
... mentioned architecture of ETA has been implemented using the conventional CMOS logic ...proposed architecture, gate diffusion input (GDI) method, is used for hardware ... See full document
11
Power and Area Efficient Error Tolerant Adder Using Pass Transistor XOR Logic in VLSI Circuits
... is error tolerant adder (ETA) is proposed to tolerate those errors and to attain low power ...adders error tolerant adder (ETA) is proposed ... See full document
5
Cassandra as a Big data Modeling Methodology for Distributed Database System
... other applications that deal with time series ...data applications because of its scalable and fault-tolerant peer-to-peer architecture , versatile and flexible data model that evolved ... See full document
9
High Performance and Area Efficient DSP Architecture using Dadda Multiplier
... high-end applications and its domains require fast operating Digital Signal Processing (DSP) ...High-performance architecture model of DSP for synthesis by mixing the optimization ...DSP architecture ... See full document
5
An Efficient Flexible Dsp Architecture For Error Tolerant Applications Employing Carry Save Arithmetic
... input operands for all the designs and, without loss of generality; we do not consider any truncation concept during the multiplications. A carry-save adder is a type of digital adder, used in computer micro ... See full document
5
An Efficient Deadlock-free NARCO based Fault Tolerant Routing Algorithm in NoC Architecture
... Traditional on-chip buses can no longer sustain the increasing demand for communication between these cores. In order to overcome the performance gap, network-on-chip is being researched. It is being considered as the ... See full document
8
Review on outlier tolerant data processing with applications
... outlier- tolerant into system modeling and some tracking prediction learning process; some outlier modeling and data recognition method were described respectively from the repeatable sampling situation of ... See full document
8
Low Truncation Error and Area Efficient Multiplier for Cryptographic Applications
... cryptographic applications like elliptic curve cryptography, RSA and other ...large error in the resultant product when fixed width output is the ...truncation error minimizing logic which greatly ... See full document
7
Efficient VLSI Architecture for Modified Blowfish Algorithm for Military Applications
... One of the example for military based applications is BEU (bulk encryption standard). This device is developed jointly by L&T and DRDO and has the following features like it sends confidential data securely ... See full document
6
Design of Approximate Adder for Error Tolerant Application
... of Error Tolerant Adder ...The Error Tolerant Adder (ETA) provides high the speed by cutting down the carry ...in applications where there is no strict requirement of accuracy or where ... See full document
5
Delay Efficient Fir Filter Architecture for Fixed And Re-Configurable Applications
... some applications, such as SDR channelizer, where FIR filters need to be implemented in a reconfigurable hardware to support multi standard wireless communication ...for efficient realization of ... See full document
8
Design of Area Efficient FIR Filter Architecture for Fixed and Reconfigurable Applications
... several applications where the coefficients of FIR filters remain fixed, while in some other applications, like SDR channelizer that requires separate FIR filters of different specifications to extract one ... See full document
8
Design of Fault-tolerant Controller for Modular Multi-level Converters.
... Automotive industry is one of the areas in which robustness of firmware design is extremely important. Each car has several modules like engine control unit (ECU), anti-lock braking system (ABS), ... that protect the ... See full document
275
A Flexible Binding Site Architecture Provides New Insights into CcpA Global Regulation in Gram Positive Bacteria
... 7 nt (Fig. 2C). According to the characteristics of this palindromic sequence, we further found two other similar palindromic sequences within the 350-bp fragment, which harbor 6- and 9-nt inverted repeats separated by 8 ... See full document
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