[PDF] Top 20 Design and Implementation of CMOS and CNT based 2:1 Multiplexer at 32nm Technology
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Design and Implementation of CMOS and CNT based 2:1 Multiplexer at 32nm Technology
... efficient implementation potential in several current and emerging technologies, the dimensions of the CNT are also small as well as the morphologies are also ...of CNT is formed via ...wall ... See full document
5
Implementation of Half Subtractor and Full Subtractor based on CNTFET
... compared based on the concert structures like Power, delay, ...CNTFET technology at 32nm ...using 32nm CNTFET and CMOS technology, shown in ... See full document
5
DESIGN AND IMPLEMENTATION OF OPTIMIZED 4:1 MUX USING ADIABATIC TECHNIQUE
... A multiplexer is the integral part of the any digital circuit and one of the most utilized ...a multiplexer has, where a multiplexer can be implemented for ...4:1 multiplexer using PFAL ... See full document
11
Design and Analysis of 5-T SRAM Cell in 32nm CMOS and CNTFET Technologies
... of Technology, Banaras Hindu University, Varanasi (now it is named as IIT-BHU) in 1999 and, at present, pursuing his second ...of Technology, Ranchi, India and ...of Technology, from 1999 to 2001 and ... See full document
6
A Darlington Pair Based CMOS Two Stage Operational Amplifier at 32nm Technology
... The operational amplifier has turned into of the bulk versatile and imperative building blocks in analog electronics. Op-Amp plays essential role in analog circuit design as logic gate plays in digital circuitry ... See full document
5
Determination of Various Performance Parameters using CMOS and CNT via 4T Schmitt Trigger
... was based over the sink ...and CNT transistors in 32nm ...the technology used was 32 nm ...trigger based over the sing logic with all ... See full document
5
CMOS Design of Area and Power Efficient Multiplexer using Tree Topology
... 180-nm CMOS technology which consists only 46 transistors. Proposed 16:1 MUX design has been implemented by using 31 NMOS and 15 PMOS ...MUX design has been shown on ...logic ... See full document
5
An Efficient Adiabatic CMOS Circuit Design Approach for Low Power Applications
... in CMOS circuit design is the large amount of power being dissipated in the ...circuitry based on adiabatic principles is a relatively new technique used to implement low power dissipating ...had ... See full document
7
Design and Analysis of CMOS and Adiabatic logic using 1:16 Multiplexer and 16:1 Demultiplexer
... William C. Athas et al [1] shown how combinational and sequential adiabatic-switching logic circuits may be constructed and describe timing restrictions required for adiabatic operation. The analyses and ... See full document
9
Power Efficient Design of Multiplexer based Compressor using Adiabatic Logic
... circuits design is increasing due to the large growth in portable digital ...power multiplexer based 4-2 compressor is designed using Positive feedback adiabatic ...compressor design is ... See full document
6
Evaluation of the Parameters of Ring Oscillators Using the CMOS and CNT 32nm Technology
... designs the consumption of the power was decreased by 28.4% at 0.9v and 54.6% at 1v [6]. Sarkar et.al 2009 have stated about the operating principle and the structure of the ring oscillators. They have described about ... See full document
5
Optimizing Low Leakage SRAM Design Based On Hetero Junction CMOS Technology
... Static random-access memory (SRAM or static RAM) is a type of semiconductor memory that uses bistable latching circuitry to store each bit. The term static differentiates it from dynamic RAM (DRAM) which must be ... See full document
8
Design, Implementation and Analysis of Error Tolerant Adder in CMOS 180nm Technology
... to design, implement and analyze the error tolerant adder (ETA) for DSP ...using CMOS 180nm technology. The design metrics such as power, delay, PDP and area in terms of transistor count are ... See full document
5
An Analysis of CMOS based Low Power 2:4 Decoder at 32nm Node using LECTOR Technique
... of technology following Moore’s Law is not a straight line as various trade-offs are to be made between dynamic power consumption, static power consumption, propagation delay, area and cost has to be ... See full document
7
Performance analysis of an energy efficient FFT processor using 32nm cmos technology
... SRAM memory block is used to store the outputs of all the radix-2 block temporarily and the stored data is read again for the next iteration. Read Only Memory (ROM) is used to storing the twiddle factors required ... See full document
6
ASIC Implementation of Multiplexer Based DAA
... Adder based DA uses pre-defined structure for ...as Multiplexer based Distributed Arithmetic (MUX based ...of Multiplexer and DA for inner product computations when both the inputs are ... See full document
8
Design and Implementation of Convolution Encoder and Viterbi Decoder
... Engling Yeo et al (2003) compared four different structures for the implementations of the ACS recursion. These inferences are applicable to the implementations of both soft and hard - decision Viterbi decoders. It was ... See full document
11
Design and Implementation of Buck Converter a...
... voltage in a laptop down to the few volts which needed by the processor. Buck converter uses SMPS topologies this topology is also called a down converter because in this output voltage is lower than the input voltage. ... See full document
6
Design of High Stability LDO Based on CMOS Technology
... 0.18um CMOS process; it includes the bandgap voltage reference with good temperature characteristic, the error amplifier of high gain and good PSRR, the power adjustment transistor and resistance feedback network ... See full document
6
Design and implementation of a co processor FPGA based numerical relay
... directional and non-directional over current relay model was carried out (Price, 2010; Khederzadeh, 2011). The detail of the MATLAB model of frequency relay was done. Testing of relay for different frequency values was ... See full document
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