Malla Reddy College of Engineering and Technology Hyderabad, India
2Ph.D.
Professor in ECE and Principal
Malla Reddy College of Engineering and Technology Hyderabad, India
Abstract:
The modern VLSI design aim at optimization of any of three parameters namely power, area and delay. To achieve this optimization many of the researchers employed CMOS technology. As the technology diverging day by day further optimization of various VLSI parameters is essential to make device smart and power comparative. As a part of optimization of area and power if we try to extend CMOS technology to nanometer range the length and width of the channel becomes too small and hence transistor loses its functionality. As alternative CMOS in nanometer scale a new technology QCA has been developed. QCA is one of the promising technologies that have been employed in modern VLSI design for optimization of power and area. This paper proposes design of multi input multi output 5 majority gate and further the same is employed in design of digital circuits namely Full Adder, RAM memory cell and reversible BCD. This paper aims at reducing area overhead and the obtained results covey fact that there is almost 50% to 60% reduction in area as compared to normal gate level design. Here all the three modules are implemented using free clock scheme and USE clock scheme and conclusions are drawn with respect to area and delay for the designed clock schemes.
I. Introduction:
Any VLSI design aims at optimization of any of three parameters namely power, area and delay. Many researchers have achieved this optimization using CMOS technology. CMOS technology gives very promising results and if we try to extend the same CMOS technology to nanometer range the length and width of the channel becomes too small and hence transistor loses its functionality. As alternative CMOS in nanometer scale a new technology QCA (Quantum Cellular Automata) has been developed. QCA is one of the promising technologies that have been employed in modern VLSI design for optimization of power and area.
The crucial feature of a QCA cell is that it possesses an electric quadrupole which has two stable orientations. These two orientations are used to represent the
two binary digits, "1" and "0". In simplest form QCA is four dot nano cell composed of four dots at corner of the square. The fig.1 given below represents a QCA cell. The four dots of quantum cell represents holes and electrons. White colored dots represent holes and black colored dots represent electrons. Thus, there are four dots in QCA quantum cell out of which two are filled with electrons and two are filled with holes and now if we apply charge, the two electrons are free to occupy any hole and thus we can have two different combinations of holes and electrons in as illustrated in fig.1. These two different combinations of holes and electrons are used to represent the two stable states binary 0 and binary 1 in QCA technology.
Fig.1: Structure of QCA
The 3-input, 1-output majority gate and the NOT gate are the basic gates of QCA technology using which we build universal gate (NAND and NOR) and then any logical circuit can be designed using universal gates. The operation of NOT gate is pretty well known to all where the output is just complement of the input and the operation of 3-input and 1-output gate is a special case where the output is the function of majority of inputs. In otherwords if the two inputs of the 3-input and 1-output gate are logic 1 the output is logic 1, conversely if the two inputs of the 3-input and 1-output gate are logic 0 the output is logic 0 and hence, sometimes it is also refereed as 3-input majority voter gate. On similar lines 5Maj gate is the promising one for area and speed optimization and the functioning 5Maj gate is similar to functioning 3Maj gate. The output of 5Maj gate will be logical‟1‟ if at least three inputs of 5Maj gate are logical „1‟. On same lines the output of 5Maj gate will be logical „0‟ if at least three inputs of 5Maj gate are logical „0‟. As a part of area and speed optimization of QCA circuits there were a lot of technological developments had taken place in the last decade and majority of them are listed here. For better understating the developments were reviewed with respect to circuits that are implemented here. Initially we take a glance at technical developments of QCA gates, Adders, RAM‟s, BCD adders, and finally ends with clocking schemes.
In [1] we can find the basics of Quantum Cellular Automota, the device architecture and the design of 3-input majority gate has laid foundation to the QCA technology and it can also be viewed that it is possible to build quantum devices which can implement logical functions as similar to conventional gates.
Binary 0 Binary 1
resonance [3].
The [4] gives details regarding the QCA tool, which provides platform where we can design and test the functionality of the QCA circuits, this tool also provides various estimates of the QCA circuits such as area, delay and so on.
Implementation of symmetric functions by using QCA gates is given in [11]. It uses 2-inputs and 2-outputs AND-NAND and OR-NOR cells designed by QCA and includes implementation of various mathematical functions, adders, subtractor‟s with the adder circuit functions and every one different combinative circuits like subtractor, multiplier, divisor, electronic device, encoder etc. can be designed, providing reduction in hardware cost as well as delay relative to other techniques present. After that a huge variety of full adder designs were presented.
Many of the have aimed to optimize area and speed. Few of them have achieved the optimization by using cross over techniques [16] multi layer designs [12], coplanar designs[19] and by employing 5Maj [20] gate and further few of them extended to build serial adders [21] showing that usage of 5Maj gates reduces computational complexity, and further more optimization with respect to area and delay can be achieved. The clocking scheme employed so far is of normal clocking scheme which can feed the clock only in forward direction and it had suffered to provide feedback paths and is not efficient with modular design and hence, a new clocking scheme which is efficient for achieving synchronous operations for QCA circuits is given in [17]. [18] discusses about the design of standard QCA cells and development of library files which aids for the simulation of QCA circuits which are build on both that is normal clock scheme as well as USE clock schemes.
The design of S-R latch, one bit full adder and 5input majority gate which were designed in QCA designer is given in [14]. The design of new RAM cell with ability of set and reset is done using 5majority gate [15] which efficient with respect area and its functional testing was carried out using QCA designer software.The technique of designing reversible circuit of BCD adder which can add two four bit numbers and can transform into BCD with effective error correction [5]. The design of reversible BCD design [6,8] given by genetic algorithm by considering don‟t cares to optimize power and garbage outputs. The concept of achieving fault tolerance by preserving parity bits in reversible one full adder is given in[7], this design is efficient with respect to garbage count, area and
constant inputs. The implementation of four bit BCD adders and binary adders using different reversible gates were presented in [10], which are efficient with respect area, garbage output count, and quantum cost. Inspite of above technical developments even still there is a scope for reduction of area and speed of BCD adders, here we present the design of one bit reversible adder using which we build four bit BCD adder with improved accuracy. For better understanding the work is organized into different sections. Section II presents the design concepts of 5Maj gate, BCD adder, full adder and RAM cell. Section III presents simulation results in comparison with the existing works
II. Circuit Design:
Here we discuss about the design of 5 input and multi output majority gate and implementation of 1-bit full adder, BCD adder and RAM cell using 5-input multi output majority gate. All these three design were done using free running clock scheme and as well as USE clock scheme. Further the same were implemented using 3-input and 1-out majority gate and conclusions were drawn with respect to various VLSI parameters.
Design of Five input and multi output majority gate:
Let us A, B, C, D, and E are the inputs of MAJ5 then the output of MAJ5 is defined by the following logical equation.
MAJ5=ABC+ABE+ABD+ACE+ACD+AED+BCE+BCD+BED+CED --- (1) The majority gate presented here has five input and two outputs. The output of the gate configured as majority or minority. As there are two outputs, the two outputs can be majority or minority, one of them can be majority and the other can be minority and vice versa. The schematic and different configurations of the majority gate are show in fig2. This feature of configuring the output increases the flexibility of the MAJ5. The configuration of output as majority or minority can be achieved by moving the last cell before the respective configuration. The feature of multi-output this MAJ5 gives additional advantages in routing, and gives flexibility in realizing more logical functions. The multi output feature of MAJ5 will reduce the number gates required to build the logic, this further can reduce the area, power consumption and the delay associated with implementation of logic function. The feature multi output of the MAJ5 will also provide reduced overhead in circuit routing, which further can reduce the parasitic effects associated with routing. The other imperative characteristic of having two outputs in MAJ5 is that, it can facilitate the flexibility for implementing of several logic functions with same design. The various logic functions that can be implemented in MAJ5 are shown in below table1.
Fig.2. Different configurations of 5Maj Table: LOGICAL FUNCTIONS OF MAJ5 GATE
A. REVERSABLE BCD ADDER
The design any digital circuits in nano technology is achieved with 3 input majority gate to optimize area and time. Further optimization in area and time can be achieved by employing above discussed 5input and multi output majority gate in the design of digital circuits. Furthermore the 5 input majority gate enjoys advantage implementation of several other logical function by fixing the inputs to logic one and logic zero which were presented in table 1. Additionally as 5 input majority gate has got multiple outputs, the additional logic functions that are present at its output can be employed based on the necessity of the design. This conserves area as well as improves the speed. The fig.3 shows flow diagram of BCD adder and the gate level schematic one bit reversible full adder which is employed to build BCD adder is given in fig.4
A BCD adder is a circuit that adds two BCD numbers and produces a sum also in BCD form. The design of BCD adder includes three blocks namely, Binary adder, above nine value detection unit and correction unit. The binary adder is employed for addition of two BCD numbers, and the sum of the two BCD number is give to the over 9 detection block and this block is used to identify if the outcome of first part is less than or equal to 9. If the output is more than 9 it produces 1 or else it produces 0. Further the output of the 9 detection block is
given to correction unit, the correction unit, based on the output 9detection block corrects the sum and finally gives its output as BCD sum.
Fig.3. Flow diagram of BCD addition
Fig.4. Gate level schematic of one bit reversible full adder
The implementation of one bit full adder shown in fig uses negative controlled toffoli gate. A negative controlled toffoli gate is one which one or more negative control lines and toggling is achieved if negative control lines are at logic 0 on the other hand positive controlling can be achieved if control line are at logic 1.There are many variants in toffoli gates here, we use n*n positive controlled toffoli gate [10]. The block level diagram of toffoli gate is given in fig.5 For sum correction we have use Six correction Logic gate. The implementation of BCD adder with the aid of reversible one bit full adder, SCL correction gate is shown in fig.6
Fig.5. Functional block diagram of Toffoli Gate
Fig.6 Block level implementation of BCD adder B. ONE FULL ADDER:
The schematic of full adder using Maj3 and Maj5 gates are given in fig.7.
where A, B and C are the inputs of the full Adder. The left most gate in the schematic (Maj3) shown is a three input majority gate which is designed Maj5 gate and hence it enjoys the advantage of multiple outputs. The output of Maj3 is given two the two inputs of Maj5 gate and remaining there inputs of Maj5 gate are A, B, and C respectively. The carry of the three bit addition is given Maj3 gate and the sum is given by Maj5 gate respectively.
Fig.7. Gate level Schematic of one bit Full adder C. RAM CELL:
The implementation of RAM cell using MAJ3 and MAJ5 is given in fig.8.
The design of RAM cell includes three MAJ3 gates and one MAJ5 gate. The MAJ3 gates employed here are of conventional design which does not have an additional add on feature of multiple outputs as that of which is employed in the design of full adder. The circuit implementation of RAM cell is pretty simple as shown in figure. It already stated that the MAJ5 has five inputs and one/two outputs, the inputs of MAJ5 are driven by the outputs MAJ3 and the other three inputs are employed for set, reset and the other is fixed to +1. The left most MAJ3 will act as and gate whose outputs are given as inputs to the other MAJ3. The other two MAJ3 also acts as simple two input AND gates with single output which are connected to MAJ5.
Fig.8. Gate level Schematic of RAM cell III. RESULTS
All the schematics of various digital designs which were discussed in the previous section were designed using QCA design tool. In this section we first present the layout of BCD adder, full adder and RAM cell, later we present the conclusions drawn with respect area and speed. Initially we compare designs that are obtained with 3MAJ gate and 5 MAJ gate with respect area and speed, later we compare results that are obtained with respect USE clock scheme with respect free running clock scheme.
The following fig.9, fig.10 and fig.11 show the design of BCD adder, RAM cell, full and adder with MAJ3 gate respectively. On the other hand the fig.12, fig.13, and fig.14. show design of BCD adder, RAM cell, and full adder with MAJ5. At a glance on comparison of the designs of 3MAJ and 5MAJ, it can be noticed that the complexity of 5MAJ designs are very less in complex to that of 3MAJ designs. In this paper the design considered are of simple and of low overhead which are employed in majority of digital circuits. On similar lines if we employ the same designed 5MAJ gate for building digital systems which are complex in nature, this can further aid in building a smart devices which are efficient with respect area and speed.
Fig.9. BCD with Maj3
Fig.10. RAM with 3Maj
Fig.11. Full adder with 3MAJ
Fig.12. BCD with 5MAJ
Fig.13. RAM with 5Maj
Fig.14. Full Adder with 5Maj
Here all the three designs were implemented with free clock as well as
Fig.15. Simulation output of full adder with free clock scheme
The fig.15 shows the simulated output of full adder with free clock scheme. The blue color signal indicates the inputs and the yellow color signal indicated the sum and carry of the full adder. From the fig. it can be inferred that the actual output of full adder almost suffers half clock pulse delay as compared to inputs. On similar lines the fig.16 shows the simulated output of the full adder with USE clock scheme, here also the blue colored wave forms indicated inputs and the yellow colored signals indicate the sum and carry of the full adder. The fig. reveals fact that the output of the full adder employing USE clock scheme suffers almost one clock period delay as compared to inputs. The comparison of both the clock schemes conveys fact that the USE clock schemes suffers more delay as compared to free running clock scheme. However the USE clock schemes has adavantage of synchronization of different operation in the complex circuits and the amount of delay can also be varied depending on the complexity of the circuit. The performance of the various design circuits with respect to delay has been presented in table.2
Fig.16. Simulation output of full adder with USE clock scheme
The table.2 show the performance in terms of area and delay. The proposed full adder with free clock has 38 cells which constitute an lowest area of 0.14 µm2 where as proposed full adder with 3 Maj has maximum cells of 160 which constitute to an area of 0.19 µm2. The proposed full adder with USE clock scheme has 130 cell which constitute an area of 0.14 µm2 which forms an intermediate between free clock design and 3 majority gate. On the same lines table show the performance of RAM interms of area and delay. The proposed RAM with free clock has 80 cells which constitute an lowest area of 0.17 µm2 where as proposed RAM with 3 Maj has maximum cells of 159 which constitute to an area of 0.20 µm2. Where the proposed RAM with USE clock scheme has 91 cell which constitute an area of 0.16 µm2 which forms an intermediate between free clock design and 3 majority gate. The values of BCD adder were given in table with respect to area and delay. The proposed BCD adder with 5Maj gates with free clock schemes has 1196 cells that consititute to an area of 2.16 µm2 and the BCD adder with 3Maj gate with free clock scheme has 1950 cells that gives area equivalent of 5.25 µm2. The BCD adder with 5Maj gate USE clock has 1496 cells that constitute to area of 3.25 µm2.
On similar lines let us take a glance at delay, the proposed full adder with free clock, USE clock and 3Maj has delay‟s of 3ns, 7ns, and 3ns respectively. The proposed RAM cell with free clock, USE clock, and 3Maj shows delay‟s of 6ns, 6ns and 9 respectively. On same lines, delay‟s of 5.7ns, 8ns and 10.5 ns delays can be observed for the design of BCD adder with free clock scheme, USE clock scheme and 3Maj gates.
Proposed (USE
Clock) 130 7 yes 0.14
Existing (3Maj gate) 160 3 No 0.19 RAM
Proposed (Free
Clock) 80 6 No 0.17
Proposed (USE
Clock) 91 6 No 0.16
Existing (3Maj gate) 159 9 No 0.20 BCD ADDER
Proposed (Free
Clock) 1196 5.7 YES 2.19
Proposed (USE
Clock) 1496 8 YES 3.25
Existing (3Maj gate) 1950 10.5 YES 5.25
The table.3 gives the comparison of different one bit adders that are designed by using free running clock scheme. The proposed design has consumed 38 cells that constitutes to an area of 0.04 µm2 and has delay of 3ns. Whereas, the design presented in [19], [20] and [14] has consumed 49,48, and 52 cells which constitute to an area of 0.4 µm2, 0.5 µm2 and 0.4 µm2 respectively. The proposed design enjoys reduction of area overhead of 29%, 26%, and 36% as compared to designs presented in [19], [20] and [14] and provides marginal improvement in speed of 1ns as compared to [19]
Table.3. Comparison of design with free running clock scheme Design Cells Delay(ns) Area(µm2)
Proposed 38 3 0.04
Sasamal
[19] 49 4 0.04
Kassa [20] 48 3 0.05
Roohi [14] 52 3 0.04
The table.4 gives details regarding implementation of the proposed designs by using USE clock scheme. The proposed adder consumes almost 215 cells lesser than the design presented in [18] and this constitutes to area reduction upto 98%.
And the proposed design is almost 2.5 times speeder than the design presented in [18]. On the other side if the we try to compare the design‟s with and without USE clock scheme the typical proposed design without USE clock scheme consumes 38 cells where the same design with USE clock scheme consumes 130 cell which constitute to increase in area overhead of 98% for USE clock implementation. On the other hand RAM design without USE clock consumes 80 cells whereas, the same RAM design with USE clock scheme consumes 91 cells and this tends to increase an area overhead of 13% for USE clock implementation.
Similarly, if we compare speeds of different design with and without USE clock schemes. The typical adder design without USE clock scheme has delay of 4ns where the same design with USE clock scheme has delay of 7ns this implies that the design employing USE clock scheme is almost 1.75 times slower than the design without USE. Whereas, RAM with and without USE clock scheme has reported the same delay of 6ns. However, the USE has many major advantages such as it can provide feedback paths, aids for development of standard libraries and designs tools and majorly avoids thermodynamics problems associated QCA circuits.
Table.4. Comparison of design with USE running clock scheme ADDER
Design Cell
s
Delay Area Proposed (Adder with
USE clock Scheme)
130 7 0.14
Reis [18] 345 18 -
RAM CELL
RAM(without USE) 80 6 0.07 RAM (With USE) 91 6 0.16 IV Conclusion
The BCD adder, one bit full adder and RAM cell were implemented with 5Maj gate with two different clock schemes, namely free running clock scheme and the USE clock scheme. Further the same were implemented using 3Maj gates and results were drawn with respect area and delay with respect to implementation of 3Maj gates and 5Maj gates as well as with respect to normal clock scheme and USE clock scheme. The implementation of full adder with 5Maj gates requires 76% less number of cells as compared to its implementation using 3Maj gates.
29%, 26%, and 36% as compared to designs presented in [19], [20] and [14] and provides marginal improvement in speed of 1ns as compared to [19]. On the other hand same sort of comparison has been carried out with respect to the design with USE clock scheme that is presented in [18] and this proves that the proposed design enjoys area overhead reduction upto 98% and finds speed improvement of 2.5 times than that of [18]. The ram implemented without USE enjoys reduction in area overhead of 13% and finds no improvement in speed of operation.
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Authors Biography:
Dr. C. Ravi Shankar Reddy has received his Ph.D., and M.Tech., degree from Jawaharlal Nehru Technological University Anantapur, Andhra Pradesh, India in 2016, and 2009 respectively. He received his B.Tech., degree from JNT University. His research interest includes Digital System, Computer Aided Design, Testing and Testability and image processing. He is currently working as professor in the department Electronics and Communication Engineering in Malla Reddy College of Engineering and Technology (Autonomous) which is permanently affiliated to JNTU Hyderabad. He has more than 25 publications that are published in National and International reputed Conferences and Journals. He is a fellow of IET.
Dr. V.S.K. Reddy, Principal, Malla Reddy College of Engineering & Technology has an experience of more than 19 years in Teaching and Industry put together.
He is alumni of IIT Kharagpur, he obtained Ph.D in the area of Multi-media Signal Processing and Communication Protocols. He is versatile in multidisciplinary specializations in Electronics & Communications and Computer Science Engineering. His laurels include more than 45 Publications in the National and International reputed Conferences and Journals. He is fellow of IETE, Life Member of ISTE and Member of IEEE. He was awarded as “Best Teacher” in three consecutive Academic years with citation and cash award. He is the recipient of “India Jewel Award” for outstanding contribution in the research in the field of Engineering and Technology.
