D-flip-flop circuits
Design and Implementation of Four Level Asynchronous Counter Using D-Flipflop
... quaternary D flip-flop with preset and clear is designed this quaternary D flip-flop is compared to previously designed binary and multi-valued D ...Proposed D ...
7
Performance analysis of D flip flop using single electron nanodevices
... It is widely known that falling feature size and increasing the transistor compactness facilitate vast improvement in the semiconductor based technology. Single-electron Technology [3] also attractive features like ...
5
Low-Power and Low-Area Dual Dynamic Node Hybrid Flip- Flop Featuring Efficient Embedded Logic for Low Power CMOS VLSI Circuits Using 120nm Technology
... Power PC 603 (Figure. 1) is one of the most efficient classic static structures. The advantages of Power PC include low-power keeper structure and low latency direct path. The keeper structure in the circuit saves the ...
6
Design and Implementation of Conventional D Flip Flop for Registers
... Different techniques are applied for power optimization in CMOS VLSI circuits. Transistor sizing is very important for the determination of circuit performance [5-6].As a result for providing reasonable ...
5
Design of Low Power Dual Dynamic Node Hybrid Flip-Flop with a Forced nMOS Circuit
... Many flip-flops have been reported in the past ...high D-Q delay even though they low power consumption, so they remain as a low power solution when speed not a ...Dynamic flip-flop structures ...
7
LOW POWER DUAL EDGE - TRIGGERED STATIC D FLIP-FLOP
... [1]. Flip-Flops are important timing elements in digital circuits which have a great impact on circuit power consumption and ...the Flip-Flop is an important element to determine the ...
7
Testing of stuck at faults in reversible sequential circuits using VERILOG HDL
... digital circuits. This paper proposes testable reversible sequential circuits based on conservative ...sequential circuits design based on conservative logic gates using fault leeway model is ...
5
Design of Power Efficient DET D-Flip Flop for Portable Applications
... VLSI circuits. The operation of low frequency circuits in the sub-threshold region stands out as the optimal method of power reduction (Wang, ...strong-inversion circuits, and so is characterized by ...
5
Novel Phase-frequency Detector based on Quantum-dot Cellular Automata Nanotechnology
... and flip-flop circuit's ...the flip-flop that examines the current and previous values of the signal and detects the edge (level to edge ...
8
SYNTHESIS OF SEQUENTIAL CIRCUITS BY REVERSIBLE LOGIC
... reversible D Flip Flop which was a realization of the conventional D Flip Flop sequential ...RS Flip Flop was used for the implementation of this ...
9
Design and Analysis of D Flip Flop Using Different Technologies
... designers. Flip flops are important state holding and timing elements in digital ...of D flip flop is much important to conclude the performance of the whole ...on flip flops but they ...
8
Low power ternary shift register using cntfets
... ternary D flip flop with preset and clear inputs is designed using Carbon Nanotube Field Effect Transistor based ternary logic ...logic circuits are (19, 0), (13, 0) and (10, 0) of diameters ...
9
Design of Sequential Circuits Using MV Gates in Nanotechnology
... logic circuits based on nanotechnology, and it is one of the replacements for designing high performance computing over existing CMOS ...sequential circuits (RS Flip Flop, D Flip ...
7
True Single Phase Clocking Flip Flop Design using Multi Threshold CMOS Technique
... Flip- flop are the fundamental building block of the digital electronics systems used in computers, microprocessors and many other types of ...systems. Flip-flop can be either simple or ...
8
Multi-Threshold Based Low Power Dual Edge Triggered Flip-Flop
... proposed flip-flop design is analyzed and compared with conventional flip-flop ...triggered flip-flop, an asynchronous Set-Reset D flip-flop and the proposed ...
10
Implementation of Reversible Sequential Circuits Using Conservative Logic Gates
... reversible D flip-flops has four control signals mC1, mC2, sC1 and ...master-slave flip-flop the values of the controls signals will be mC1=0 and mC2=1, sC1=0 and ...
6
Comparative Analysis of D Flip Flops Using Different Technologies
... designers. Flip- flops or the data storage elements are almost an essential component of every sequential ...various flip-flops, D flip- flop is commonly ...the D input at a ...
5
Reduction of Power and Delay usingSingle Event Transient Suppressor forSequential Elements
... sequential circuits SET suppressor circuit can be used for feeding clock signals which reduces glitches thereby reducing the power ...ordinary D flip flop circuit and another D ...
8
Optimization Of Power For Sequential Elements In Pulse Triggered Flip-Flop Using Low Power Topologies
... or Flip-Flop can store one bit of ...and flip-flops is that for latches, their outputs are constantly affected by their inputs as long as the enable signal is ...change. Flip-flops, on the ...
6
A Greedy Heuristic Algorithm for Flip-Flop Replacement Power Reduction in Digital Integrated Circuits
... of flip-flops, first build a combination table before actually merging two ...of flip-flops which are 1-, 2-, and 3-bit first to separate the flip-flops into three ...3-bit flip-flops is not ...
11