Hardware and Architecture
High speed hardware architecture for implementations of multivariate signature generations on FPGAs
... high-speed hardware architecture for signature generations of a multivariate scheme is proposed in this ...high-speed hardware architecture based on the above improvements on an Altera Stratix ...
9
FPGA implementation for the hardware architecture used in cyclostationary detector
... Cognitive radio is one of the modern techniques which is evolved for utilising the unused spread spectrum effectively in wireless communication. Sensing of spectrum holes in a particular spectrum is one of the important ...
9
Hardware Architecture of High Speed HEQ for Image Enhancement
... the hardware architecture of high speed HEQ, which can process full HD image and can be incorporated in small size FPGA, is ...proposed architecture, a reference C was constructed and compared with ...
6
A Hardware Architecture for Scheduling Complex Real-Time Task Sets
... complete hardware architecture that implements slack stealing in hardware using an optimal algorithm redesigned to be implemented efficiently in ...of hardware design, the algorithm involves ...
13
Hardware Architecture of a Low-Cost Scalable Energy Monitor System
... This rapid growth of IoT implementations didn’t come without its growing pains. While its applications multiply, there hasn’t been a consensus on what a standard architecture common to all IoT systems ought to ...
5
Design of parallelized HDWT Hardware Architecture with an Increased Throughput
... Cosine Transforms (DCTs), DWT features progressive image transmission by quality or resolution, lossy and lossless compressions, region of interest (ROI) encoding, and good error resilience [10]. Yusong Hu, Viktor K. ...
6
High-Throughput Hardware Architecture for the SWIFFT / SWIFFTX Hash Functions
... The overall hardware architecture for SWIFFT is shown in Figure 5. We opted for the BlockRAM-based implementation of the MAC multipliers (the first ap- proach) having one cycle latency. The input message is ...
17
Modular Hardware Architecture for Somewhat Homomorphic Function Evaluation
... a hardware architecture for all building blocks re- quired in polynomial ring based fully homomorphic schemes and use it to instantiate the somewhat homomorphic encryption scheme ...Our architecture ...
22
A Hardware Architecture of Particle Swarm Optimization
... speed, hardware implementations of MSPSO are ...are Hardware/Software co-design implementation [10], [11], parallel hardware implementation [12]-[14], and serial hardware implementation [15], ...
9
Software and Hardware Architecture of H 264/AVC Decoder
... pipeline architecture to implement the ...of hardware encoder implementation is given in ...and hardware/software ...The hardware acceleration module includes motion compensation, inverse ...
8
Lossless Data Compression and Decompression Algorithm and its Hardware Architecture
... two-stage architecture for lossless data compression applications, which uses only a small-size dictionary, is ...compression architecture combines the PDLZW compression algorithm and the AH algorithm with ...
7
Reconfigurable Signal Processing and Hardware Architecture for Broadband Wireless Communications
... a hardware platform for the proposed transceiver and identify the reusable common ...receiver architecture for the down- link ...that hardware and software sharing is possible for these ...
10
VLSI Hardware Modelling Of Multifunction GF Architecture for Cryptographic Devices
... Abstract — this paper presents a hardware structure for polynomial binary-to-residue number system (PRNS) conversion using parallel field structures. This structure is based only on polynomial multipliers along ...
8
Hardware Architecture for a Message Hiding Algorithm with Novel Randomizers
... Zhang LSB algorithm delivers several advantages. This algorithm can resist statistical analyses and enables the usage of LSB in a secure way. Therefore, it is more appropriate for hardware implementation. ...
8
Flexible and an Efficient Hardware Architecture for A Secured Data Communication
... This architecture provides the secured communication in internet where the speed of the transmission would be high as there is combination of both the symmetric and asymmetric encryption ...
7
Enabling centralized access to a reactive architecture for hardware control systems
... The Thales sensor management architecture is a reactive architecture that matches the defi- nition of a reactive architecture as introduced in Chapter 1. A component-based development method is ...
61
Novel DHT Algorithm Implementation Using Sharing Multipliers
... modular architecture is ...VLSI architecture for ...the hardware complexity can be significantly reduced the number of multipliers being very small, significantly less than that in ...small ...
10
Meet the Challenge of Teaching Computer Organization and Architecture----Physical Computing
... and architecture is a very important ...computer hardware and electronics for the fact that computer organization & architecture is the only course that exposes students to the ...the ...
14
Volume 44: OCL and Textual Modelling 2011
... The Renesas SH2 model was created collaboration with B2i Automotive Engineering 1 . The work was carried out by a student in master’s degree of computer science and electronic engi- neering, during a six-month ...
17