power data from ICC with clock gating
A Low Power Clock Gating Based On Look Ahead Clock Gating
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Flip-Flop Grouping in Data-Driven Clock Gating for Dynamic Power Management
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Power Saving for Merging Flip Flop Using Data Driven Clock Gating
6
ABSTRACT: We propose new technique for clock gating. Clock gating is helpful for reducing power consumed in digital
9
Dynamic Power Reduction Using Clock Gating: A Review
5
Low Power VLSI Design using Clock Gating Technique
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Subword Partition based Data Driven Clock Gating Scheme for Low Power VLSI Design
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Reduction of Power Dissipation in 32bit RISC Microprocessor using Clock Gating
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Power Optimization of Linear Feedback Shift Register Using Clock Gating
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Power Efficient Implementation of Streaming Applications using low power Clock-Gating method on FPGAs
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Low power 130 nm CMOS Johnson Counter with clock gating technique
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A Design and Analysis of Low Power Linear Feedback Shift Register with Clock Gating
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Low-power flip-flop using internal clock gating and adaptive body bias
161
Power Harvesting and Area Efficient Clock Gating Method for a De Composed MUX Controller
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Improve Performance Of Low Power And Low Voltage Double Tail Comparator By Clock Gating
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Effect of clock gating in conditional pulse enhancement flip-flop for low power applications
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LOW POWER DESIGN OF DIGITAL SYSTEMS USING ENERGY RECOVERY CLOCKING AND CLOCK GATING
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Novel Methods of Clock Gating Techniques: A Review
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Vector processing-aware advanced clock-gating techniques for low-power fused multiply-add
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Analysis of Clock Gating Applications for Energy Efficient Implementations on FPGA’s
5