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signal processors

Comprehensive  Efficient  Implementations  of  ECC  on  C54xx  Family  of  Low-cost  Digital  Signal  Processors

Comprehensive Efficient Implementations of ECC on C54xx Family of Low-cost Digital Signal Processors

... We present comprehensive yet efficient implementations of ECC on fixed-point TMS54xx series of digital signal processors (DSP). 160-bit prime field ECC is implemented over a wide range of coordinate ...

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Real-Time Adaptive Phase-Lead Controller for Maglev Systems Using Digital Signal Processors*

Real-Time Adaptive Phase-Lead Controller for Maglev Systems Using Digital Signal Processors*

... Abstract-This paper addresses real-time adaptive Phase-lead controller for maglev systems using digital signal processors (DSP). With an adaptive phase-lead controller, the DSP automatically updates the ...

6

Architectural Review: Evolution of Embedded Digital Signal Processors

Architectural Review: Evolution of Embedded Digital Signal Processors

... world signal processing the additional range provided by floating point is not needed, and there is a large speed benefit and cost benefit due to reduced hardware ...

6

Area Delay Power Efficient Carry Select Adder  for Modern Signal Processors

Area Delay Power Efficient Carry Select Adder for Modern Signal Processors

... The design shows the basic 8 bit addition procedure which includes 8-bit data, a 8-bit BEC logic and 16:8 mux. The addition is performed for Cin=0 and for Cin=1.For Cin=0 the addition is performed by ripple carry adder ...

6

Multi-Channel Neutron Emission and Triton Burn-up Measurement on JT-60U Using Digital Signal Processors

Multi-Channel Neutron Emission and Triton Burn-up Measurement on JT-60U Using Digital Signal Processors

... rate, a digital signal processing (DSP) system was devel- oped for neutron detectors [3, 5]. In this DSP system, out- put pulses from the anode of a photo multiplier tube (PMT) of a detector are recorded as a ...

5

Floating-to-Fixed-Point Conversion for Digital Signal Processors

Floating-to-Fixed-Point Conversion for Digital Signal Processors

... for processors with instruction-level parallelism (ILP) capabilities, the overhead due to scaling op- erations depends on the scheduling step and cannot be easily evaluated before the code generation ...

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Teaching Challenge in Hands-on DSP Experiments for Night-School Students

Teaching Challenge in Hands-on DSP Experiments for Night-School Students

... digital signal processors, strong software development, such as real-time DSP algorithms, and programming skills are also ...digital signal processors for ...

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A Reconfigurable Rls Filter For Hearing Guide Systems

A Reconfigurable Rls Filter For Hearing Guide Systems

... digital signal processors has increased, adaptive filters have become much more common and are now routinely used in devices such as mobile phones and other communication devices, digital cameras, and ...

5

Power estimation on functional level for programmable processors

Power estimation on functional level for programmable processors

... One possible straight forward power estimation approach on DSPs is the so-called Physical-Level Power Analysis methodology. This approach is based on the analysis of the switching activity of all transistors of the DSP ...

5

A Fast and Efficient On-Line Harmonics Elimination Pulse Width Modulation for Voltage Source Inverter Using Polynomials Curve Fittings

A Fast and Efficient On-Line Harmonics Elimination Pulse Width Modulation for Voltage Source Inverter Using Polynomials Curve Fittings

... To implement the on-line HEPWM, it appears that most researchers opted for the digital signal processors (DSP). This is inevitable, as HEPWM algorithms are generally complex and significant computing power ...

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Design and Implementation of Carry Tree Adders using Low Power FPGAs

Design and Implementation of Carry Tree Adders using Low Power FPGAs

... Abstract— The binary adder is the critical element in most digital circuit designs including digital signal processors (DSP) and microprocessor data path units. As such, extensive research continues to be ...

5

PARALLEL ARRAY MULTIPLIER DESIGN TECHNIQUES

PARALLEL ARRAY MULTIPLIER DESIGN TECHNIQUES

... Multiplication is the basic building block for several DSP processors, Image processing and many other. Over the years the computational complexities of algorithms used in Digital Signal Processors ...

10

Application of Artificial Neural Network and Binary Logistic Regression in Detection of Diabetes Status

Application of Artificial Neural Network and Binary Logistic Regression in Detection of Diabetes Status

... Artificial Neural Network (ANN) modeling, a paradigm for computation and knowledge representation, is originally inspired by the aspect of information processing and phys- ical structure of the brain with a web of neural ...

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Design Methodology for Low Error Fixed Width Adaptive Multiplier

Design Methodology for Low Error Fixed Width Adaptive Multiplier

... Multiplication is an important operation in many algorithms used in scientific computations such as Digital Signal Processing (DSP). The computational complexities of algorithms used in Digital Signal ...

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Median and Morphological Specialized Processors for a Real Time Image Data Processing

Median and Morphological Specialized Processors for a Real Time Image Data Processing

... The vision signal real-time processing for the needs of control systems require high computation powers. Therefore, meth- ods for fast implementation of the processing algorithms have to be looked for. In the ...

7

Digital Control of Permanent Magnet Synchronous Motor

Digital Control of Permanent Magnet Synchronous Motor

... Hardware implementation of FOC is proposed and implemented using Digital Signal Processor on Code Composer Studio v.5.2 with Real Time Debugging on a 24 V Permanent Magnet Synchronous Motor. Expected results over ...

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Analytical Modelling of Parallel Programs

Analytical Modelling of Parallel Programs

... Abstract— A parallel program should be evaluated to determine its efficiency, accuracy and benefits. This paper defines how parallel programs differ by sequential programs. A brief discussion on the effect of increasing ...

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A QoS Latency Aware Event Stream Processing with Elastic FaaS

A QoS Latency Aware Event Stream Processing with Elastic FaaS

... The above formula can be directly applied for adaptively provisioning the individual systems such as VMs, Containers, and so on. However, in systems like FaaS, this formula cannot be directly applied, since in FaaS under ...

7

Graph Theory and Its Applications

Graph Theory and Its Applications

... Interconnection network for five processors (a complete graph).. Interconnection network for eight processors (a cube Q 3 )..[r] ...

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Evaluation Air Pollution Due to Transient Emissions

Evaluation Air Pollution Due to Transient Emissions

... Abstract- This paper considers the design of wireless communications systems which are implemented as highly integrated embedded systems comprised of a mixture of hardware components and software. An introduction part ...

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