[PDF] Top 20 An Efficient Majority Logic Fault Detection to reduce the Accessing time for Memory Applications
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An Efficient Majority Logic Fault Detection to reduce the Accessing time for Memory Applications
... Some multi error bit corrections Codes are reed Solomon codes and Bose- Chaudhuri- Hocquenghem codes, but in which the algorithm is so complex and it is iteration based. The decoders too decode in fixed rate and so it ... See full document
5
ASIC Implementation of MLDD for Error Detection and Correction
... an efficient majority logic fault detection to reduce the accessing time for memory applications using the quasi cyclic LDPC ...traditional ... See full document
8
An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]
... Configurable Logic Blocks (CLBs) and programmable switch matrices, surrounded by programmable input/output blocks on the ...many applications such as networking, storage systems, communication, and adaptive ... See full document
8
EFFECIENT MAJORITY LOGIC FAULT DETECTOR/CORRECTOR USING EUCLIDEAN GEOMETRYUSING LOW DENSITY PARITY CHECK CODES
... Error detection in memory applications was proposed to accelerate the majority logic decoding of difference set low density parity check ...as majority logic decoding can ... See full document
6
EFFICIENT FAULT DETECTION CODES
... SRAM memory failure rates are increasing significantly, thereby raising a major reliability problem for many ...with majority logic decoding. Majority logic decodable codes are suitable ... See full document
13
Novel Correction and Detection for Memory Applications
... as memory applications are concerned the soft errors and single event upsets are always a matter of ...an efficient Multi Detector/Decoder (MLDD) for fault detection along with ... See full document
8
FPGA IMPLEMENTATION OF EUCLIDEAN GEOMETRY LOW DENSITY PARITY CHECK (EG-LDPC) CODES FOR ERROR CHECKING IN MAJORITY LOGIC DECODING
... protect memory cells, which are more susceptible to soft errors. These memory cells are to be protected with effective error correction ...codes. Majority logic decodable codes are suitable ... See full document
7
Error Identification and Correction for Memory Application using Majority Logic Decoder and Detector
... new memory storage technology which may be used for memory applications such as aerospace, nano-bioengineering, ...Error detection and correction are main issues in the memory which ... See full document
6
Architecture with reduced Latency And Complexity For Matching of Data Encoded With Hard Systematic Error- Correcting Codes
... a Majority Logic Decoder/Detector (MLDD) for fault detection along with correction of fault, suitable for memory applications, with reduced fault detection ... See full document
8
Novel Correction and Detection for Memory Applications
... as memory applications are concerned the soft errors and single event upsets are always a matter of ...an efficient Multi Detector/Decoder (MLDD) for fault detection along with ... See full document
8
CCBKE Session Key Negotiation for Fast and Secure Scheduling of Scientific Applications in Cloud Computing
... scientific applications, these operations can be very ...most efficient cryptological solution in protecting data confidentiality and integrity, especially in data-intensive scientific applications ... See full document
16
Cost Efficient Fault Tolerant Decoder in Reversible Logic Synthesis
... criteria which has been presented for the first time in this paper. Any don't care inputs are considered as Garbage Sink which does not effect on any functional outputs or propagates garbage value to output line. ... See full document
6
Fault Detection in Hydraulic System Using Fuzzy Logic
... fuzzy logic over conventional method like Wald’s sequential test [4] has several ...no fault to faulty ...Fuzzy logic is a good option because there is no general mathematical model available which ... See full document
6
Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller
... This LDR instruction fetches the 32-bit word 0x00000000 stored at the test_data label and stores it in register R0 . A fault is detected on the third bit if, for instance, the actual value stored in register R0 is ... See full document
22
Future Stock Price Prediction using LSTM Machine Learning Algorithm
... forecasting. Time Series Forecasting is basic for share price forecasting and other financial model ...intelligent time series prediction systems are ...not efficient enough in ...for ... See full document
5
Detection of Fault-injection Attacks for Cryptographic Applications
... the partial product P k Q l together. The simplest implementation requires an N-bit adder and take M cycles to generate the output. Another implementation of multiplier is so called adder array multipliers which achieve ... See full document
7
Efficient Bio inspired Method for Disaster Monitoring in Wireless Sensor Networks Using Improved PSO
... Recently many methods presented for efficient and effective management of disasters in WSNs, however there is still scope of improvement. The PSO method was previously used for disaster management, however as this ... See full document
7
Fault Tolerant Circuit Design using Evolutionary Algorithms
... fewer logic gates and fewer number of gates contained in the longest signal chain of the circuit is usually preferable, the main purpose in this paper is to investigate the capacity of fault recovery using ... See full document
6
Vibration fault detection and classifaction based on the fft and fuzzy logic
... the time to frequency domain based on the FFT, as shown in Figure-1 (Muralidharan and Sugumaran, ...vibration fault, thus, the signal modifying to generating the envelope signal of the FFT (Marichal et ... See full document
5
Fault Secure Encoder and Decoder for Nano Memory Applications
... proposed fault tolerant encoders and decoders so far, use the conventional fault tolerant scheme ...(e.g., logic replication or concurrent parity prediction) to protect encoder and corrector ... See full document
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