[PDF] Top 20 WRL 95 2 pdf

... Most circuits are better described by programs rather than drawings. Programs are more con- cise than drawings and much easier to modify. Figure 2 shows an example of a cell generator for a register. This ... See full document

... groups. The first group did not use the X11 window libraries, while the second group did. Programs that are part of the SPEC92 benchmark suite are indicated by check marks. These tables show the percentage of ... See full document

... Combining all these ideas results in a system similar to one developed at Xerox PARC [1, 2]. With their schematic editor, parameterized cells are designed using the full power of a program- ming language. One ... See full document

... The Shasta protocol has been implemented on our prototype cluster and is fully functional. The cluster consists of a total of sixteen 300 MHz Alpha processors connected through the Memory Channel [10]. We present ... See full document

... Hardware is required to control the issuing instructions, to track data flow, and to recover from exceptions. A number of techniques have been used to implement this functionality. Scoreboarding, a technique first ... See full document

... Figure 1 executing on a model such as weak ordering (WO). In this example, it is sufficient to maintain only the following orders for correctness: (1) on P1, maintain program order between the write to Head and ... See full document

... 4.2BSD follows the model described in section 4.1, and depicted in figure 6-2. The device driver runs at interrupt priority level (IPL) = SPLIMP, and the IP layer runs via a software inter- rupt at IPL = SPLNET, ... See full document

... Approximately six weeks before the 1994 general election, a group of researchers from several of Digital’s research labs arranged with the California Secretary of State’s office to provide online election returns and ... See full document

... about 95%. Even with an idle timeout of just 2 minutes, the election service would have achieved a 95% hit rate; the corporate server would have achieved ... See full document

... Figure 2 shows two examples of converting a wire width and space into a centerline ...width 2⋅spacing+width is even, as in the second example in the figure, the bloat is asymmetric; we choose arbitrarily to ... See full document

... At this point, the scheduler has filled as many of the memory stalls and coprocessor stalls in the basic block as it can.* It then looks to see if the block ends with a branch whose slot[r] ... See full document

... The low general level of sharing of file blocks among client workstations lead us to conclude that a cache coherence mechanism is not as expensive to provide as was previously thought. In our data, most applications use ... See full document

... and require much more buffer memory; (3) the performance gains are limited because a datagram cannot be larger than the MTU of the first-hop network and because a maximum size must be enforced to provide a limit on ... See full document

... Because our tracker matches the current frame with the first frame, the drift problem does not seem to occur. This is evident from the approximately constant pixel errors with increasing number of frames. To see if the ... See full document

... I implemented this global register allocator in a code generator used for Fortran, C, and Modula-2, and , my colleagues have used it to port the Unix operating system to the new machine. To learn how well it works ... See full document

... Figure 3-10 shows the decoding of the syndrome bits for a half-line. Note that the syndrome bits are complemented in the ErrorLog register, and that this table applies to the uncomplemented syndrome. For single-bit ECC ... See full document

... are 2 distinct regions of energy consumption here - the period when the one of the bitlines is discharging, and the period when the bitlines have reached a stable nal value (after the bitline has completed ... See full document

... The original values of the control points for each invocation are compared to the new values, and, if they vary, the using statements associated with these invocations each get reexecute[r] ... See full document

... We tested five register management schemes: compile-time, Steenkiste’s mixed strategy, link-time with use estimates, 16 fixed-sized windows of 8 registers, and variable-sized windows usi[r] ... See full document

... List of Figures Figure 1: Points for measuring load Figure 2: Experimental configuration Figure 3: Packet generation process Figure 4: Total bit rate Figure 5: Standard deviation of bit [r] ... See full document