all digital delay-locked loop
A Static Phase Offset Reduction Technique for Multiplying Delay Locked Loop
8
Glitch free NAND based DCDL in phase locked loop application
5
Delay-Locked Loop Using 4 Cell Delay Line with Extended Inverters
5
ELECTRONIC INFORMATION SHARING BETWEEN PUBLIC UNIVERSITIES AND MINISTRY OF HIGHER EDUCATION AND SCIENTIFIC RESEARCH: A PILOT STUDY
7
Design and Simulation of Low Power Consuming Digital Controlled Oscillator in All Digital Phase Locked Loop
6
Extended Lock Range Zero Crossing Digital Phase Locked Loop with Time Delay
6
DESIGN OF CONFIGURABLE MULTIPHASE CLOCK GENERATION AND FREQUENCY MEASURING CIRCUIT
8
Performance evaluation of the time delay digital tanlock loop architectures
30
A Low Power VLSI Design of an All Digital Phase Locked Loop
5
FFT Analysis, Simulation of Computational Model and Netlist Model of Digital Phase Locked Loop
16
A Digital Phase Locked Loop based System for Nakagami m fading Channel Model
8
Design and Implementation of Digital Demodulator for Frequency Modulated CW Radar (RESEARCH NOTE)
10
DDS Based Phase Locked Loop
9
Phase Locked Loop Test Methodology
38
STUDY AND IMPLEMENTATION OF PHASE LOCKED LOOP
5
Design of CMOS Phase Locked Loop
7
Implementation of Low Power All Digital Phase Locked Loop
7
A Digital Phase Locked Loop Speed Control of Three Phase Induction Motor Drive: Performances Analysis
8
Efficient 500 MHz Digital Phase Locked Loop Implementation sin 180nm CMOS Technology
9
Fixed Point Iteration Chaos Controlled ZCDPLL
11