Design and implementations

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ICT And Design: Challenges And Implementations In Kaduna State University

ICT And Design: Challenges And Implementations In Kaduna State University

2012, p.3) Research study was conducted by (Hosseini, et al. 2012) implementation of ICTs framework for best practice as methods of development for productivity and industries standards for globalizations. Web develops applications and internet connectivity has rapidly increased and attracts government attentions on ICT project to improve learning and teaching efficiency for students and lectures (Wang et. al. 2007, p.1-2). This drawn the attentions of educational institutions to implement ICTs applications theoretical and technical concepts into practice to improve teaching and learning process (Ul-Amin, 2009). A proposed strategy for ICT development by international organization for standardization (ISO) applied various concepts and skills of different scientist in which includes theoretical foundations and technical for ICTs framework (Parma, 2009). Integration of ICT architectures is process whereby a holistic information systems process, information technology and ICTs (IS, IT and ICTs) problems are describes in technological manners and organization structural designs that make technology work efficient. In turn design is a creativity and knowledge that people are admired and value to pay for and problem solving consists of various processes, procedures, requirement and engineering ICT tools and services implementations for best practice (Fomin, 2008, p.2). ICT framework research paper (Vorisek, 2011) describes ICT layers functionality as services and management that integrate TOGAF, SPSPR and ITIL model architecture for computing resources to the needs of organization addressed. International organization for standardization (IOS) has seven layers architectures which serve as reference guides model for network administrator to setup network. A research study of technical architectures that serve as internal Blueprint for ICTs systems with emphasis of four network layer services integrations (Danish Defence Target Architecture, 2011, p.5-10).
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Hardware/Software Co-Design Architecture and Implementations of MIMO Decoders on FPGA

Hardware/Software Co-Design Architecture and Implementations of MIMO Decoders on FPGA

Hardware/software co-design architecture for two typical MIMO lattice decoding algorithms has been designed and implemented in this thesis. The closest lattice point searching procedure is partitioned into the FPGA-based hardware modules. And a MicroBlaze soft core is used for the channel matrix preprocessing and R/I decomposition. Three levels of parallel structures are designed in this co-design architecture to improve the decoding rate. The overheads involved in these parallel structures are also analyzed. The proposed architecture is prototyped on the Xilinx XUP Virtex-II Pro developing board with an XC2VP30 FPGA. The experimental results show that the AV and VB based decoders can reach up to 81.5 Mbps and 37.3 Mbps decoding rate respectively at 20 dB Eb/N0 for a 4 × 4 MIMO system with 16-QAM modulation, which are among the fastest MIMO decoders to the author’s knowledge. They are about 37 and 187 times faster than their respective implementations in a DSP processor. The BER performance of the experimental prototype matches with the software simulation results.
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User-Centered Design in Procured Software Implementations

User-Centered Design in Procured Software Implementations

In addition to recognizing that SharePoint migrations required attention to change management processes as much as custom development projects that included UCD do, the author also quickly learned that revamping each departments’ information architecture would require a greater level of effort and guidance from usability specialists than originally expected. For example, some SharePoint sites initially went live without support from a usability specialist, and received negative feedback from staff. This feedback was enough to halt user adoption and the department’s migration, and so the author was called in to investigate what the problems were. After conducting a few interviews, it was discovered that users were confused by the creation of both company-facing and internal sites for a single department (when there was no need for the separation given the user base’s information needs), as well as mixed-model items appearing in the left navigation bar’s Site Hierarchy (e.g., application, team, and project names in one list). (See Figure 4. Note that the Systems Services company-facing site design
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Design of Improved Distributed Canny Edge Detection Algorithm (IDCEDA) and its VLSI Implementations

Design of Improved Distributed Canny Edge Detection Algorithm (IDCEDA) and its VLSI Implementations

Field Programmable Gate Array (FPGA) is a general purpose programmable device that can be programmed by end user for different applications as per requirement unlike traditional Application Specific IC (ASIC). The main important aspect of FPGA can be easily reprogrammed after deployment into a system. FPGA can be programmed by downloading bit-stream into on chip random access memory. FPGA Provides configurable resources used to implement high level arithmetic and logic functions. The resources include dedicated DSP blocks, MAC units, dual port memories, LUTs, registers, tri-state buffers and multiplexers. It provides high parallelism, distributed memory architecture and high cock rates i.e. 500 MHZ, hence it is suitable for wide range of applications. Apart from the advantages FPGA’s can also have some drawbacks such as it consumes more power and more area for its programmable part than ASIC. Finally FPGA’s and ASIC can provide various solutions for the designer and carefully evaluated before selecting the device. Fig.1. gives the future metrics of FPGAs for various Applications. This graph can be taken as reference for predicting the importance of FPGA and its internal architectural blocks shown in Fig.2. The implementation of image processing algorithms on FPGA is a three step process[6].first, knowing the complete description about both algorithm and software implementation. Second, design should be optimized with respect algorithm (e.g. using transformation techniques) and hardware part (e.g. using more advanced fixed point blocks). Finally we evaluate the complete design for performance parameters like speed, resource utilization, image quality and reliability of the algorithm.
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L}ow Power Architecture Design of De-Blocking Filter and Hardware Implementations in H.264/{AVC

L}ow Power Architecture Design of De-Blocking Filter and Hardware Implementations in H.264/{AVC

Once filtering of edge8 is completed, the transposition buffer can be switched to the next 4x4 basic block for storing the filtered pixels of edge10. For the traditional filtering order standardized in H.264/AVC shown in Fig. 5 (a), it does not reuse data well and requires more memory or transposition buffers to store filtered pixels. For the order of edge filtering 1, 6, 10, 3, 7, 11, 17, 22, 26, 19, 23, 27, 33, 35, 41, and 43 of the different 4x4 blocks, we need transposition buffers to transpose data from the row to column to intermediately store pixels for the vertical filtering on horizontal edges. Because transposition buffers require at least 4 clock cycles to write the filtered pixels back to the current 4x4 block in our 4-stage pipeline, this filtering strategy does not proceed immediately with vertical filtering followed by horizontal filtering due to the delay of transposition buffer. By observing the filtering order carefully, we can observe that on some 4x4 blocks, the transposition buffers encounter long waiting times from edge order 5 to 20, 9 to 24, 14 to 28, and 15 to 29 to serve edge20, 24, 28, and 29, respectively. Therefore, we adopt upper neighbor SRAM to reuse the data in the design for storing the filtered results of B0, B1, B2, and B3 to be later used for edge order 20, 24, 28, and 29 as depicted in Fig. 6. Compared to Ke Xu et al. [7], we save transposition buffers for storing the upper MBs.
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Low Power, Low Phase Noise Based Phase Locked Loop and Its Design Implementations

Low Power, Low Phase Noise Based Phase Locked Loop and Its Design Implementations

C. Voltage Controlled Oscillator Design and Working. In our design of PLL, We designed the PLL using a very popular scheme that is current starved ring oscillator (CSVCO) [3]. No of inverters we used is this design is 5. Basically, a VCO [5] is termed as a circuit whose oscillation frequency is controlled by an input voltage provided to it. Design of VCO is a cascaded set of inverters. The final output of the inverter is feedbacked to the design circuit.

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Stochastic Design of Enhanced Network Management Architecture and Algorithmic Implementations

Stochastic Design of Enhanced Network Management Architecture and Algorithmic Implementations

The paper is focused on available server management in Internet connected network environments. The local backup servers are hooked up by LAN and replace broken main server immediately and several different types of backup serv- ers are also considered. The remote backup servers are hooked up by VPN (Virtual Private Network) with high-speed optical network. A Virtual Private Network (VPN) is a way to use a public network infrastructure and hooks up long-distance servers within a single network infrastructure. The remote backup servers also replace broken main severs immediately under the different conditions with local backups. When the system performs a mandatory routine mainte- nance of main and local backup servers, auxiliary servers from other location are being used for backups during idle periods. Analytically tractable results are obtained by using several mathematical techniques and the results are demon- strated in the framework of optimized networked server allocation problems. The operational workflow give the guide- lines for the actual implementations.
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Single-Cycle  Implementations  of  Block  Ciphers

Single-Cycle Implementations of Block Ciphers

Finally, recommendations for the design of low-latency algorithms follow from these remarks. When focusing on low latency, having an unrolled design, like PRINCE, gives significantly better results. Iterated SP networks also perform well: the delay of small S-boxes is not very high and the permutation layer can essentially be implemented for free. The number of rounds should be as low as possible, while still maintaining an acceptable level of security. Small S-boxes are a nice component, as they have low latency as well as good area performance. Lastly, the general design rule to use boolean operations in hardware designs also applies here.
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On The Security Evaluation of Partial Password Implementations

On The Security Evaluation of Partial Password Implementations

The design of a secure and efficient user authentication scheme is one of the major concerns for most enterprises and organizations. A significant amount of money, time and e↵ort are invested every year to carry out research in this direction. Ac- cording to Cybersecurity Ventures, the U.S Government has invested more than $50 million over the past four years in Multi-Factor Authentication (MFA) tech- niques, aiming to improve a simple password-based authentication scheme [7]. Additionally, many academic studies in the past studied extensively the security and usability of password-based authentication techniques [1,3,9,13,14].
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Hardware Implementations for Symmetric Key Cryptosystems

Hardware Implementations for Symmetric Key Cryptosystems

Another initiative for designing secure stream ciphers is the LTE mobile technology. LTE is being established as the fourth generation (4G) mobile technology, where a flat all Internet Protocol infrastructure has been adopted [34]. This has changed the threat model of the 4G mobile domain to include the security issues which are applied to the IP-networks [34]. Ac- cordingly, there is a continuous e ff ort demonstrated by the security specification group of the third generation partnership project (3GPP-TSG) [1] to address these security threats [34]. The cipher suite of 4G LTE consists of two stream ciphers, SNOW 3G and ZUC, and the block cipher AES in the counter mode [11, 7]. It is noted that the randomness of the key-streams generated by the 4G LTE cryptographic algorithms is hard to analyze and, more importantly, some weaknesses concerning these ciphers have already been discovered [87, 21]. Further- more, some security flaws in the LTE integrity protocols have been recently recognized [90]. The authors of [34] propose confidentiality and integrity protection schemes for securing the 4G network domain against the attack in [90]. These schemes are based on the WG-16 stream cipher. The WG-16 o ff ers the proved randomness properties of the WG family of ciphers [34]. In addition, it is secure and resists to all known attacks [34]. The only WG-16 hardware design, which uses NB, is presented in [35]. This design is based on composite field arithmetic and properties of the trace function in the tower field representation.
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VerMI:  Verification  Tool  for  Masked  Implementations

VerMI: Verification Tool for Masked Implementations

Abstract. Masking is a widely used countermeasure against Side-Channel Attacks (SCA), but the implementation of these countermeasures is chal- lenging. Experimental security evaluation requires special equipment, a considerable amount of time and extensive technical knowledge. So, to automate and to speed up this process, a formal verification can be per- formed to asses the security of a design. Multiple theoretical approaches and verification tools have been proposed in the literature. The majority of them are tailored for software implementations, not applicable to hardware since they do not take into account glitches. Existing hardware verification tools are limited either to combinational logic or to small designs due to the computational resources needed.
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Photonic Delay Systems as Machine Learning Implementations

Photonic Delay Systems as Machine Learning Implementations

The next direction for improvement would be to rethink the design of the system from a machine learning perspective. The current physical setup on which we applied backprop- agation finds its origins in reservoir computing research. As we argue in Section 2, the system can be considered as a special case of recurrent network with a fixed, specific con- nection matrix between the hidden states at different time steps. In the reservoir computing paradigm, one always uses fixed dynamical systems that remain largely unoptimized, such that in the past this fact was not particularly restrictive. However, given the possibility of fully optimizing the system that was demonstrated in this paper, the question on how to redesign this system such that we can assert more control over the recurrent connection matrix, and hence the dynamics of the system itself, becomes far more relevant. Currently we have a fixed dynamical system of which we optimize the input signal to accommodate a certain signal processing task. As explained at the end of Section 3.2, it appears that backpropagation can currently only leverage the recurrence of the system to a limited de- gree, when using a single delay loop. Therefore it would be more desirable to optimize both the input signal and the internal dynamics of the system to accommodate a certain task. Alternatively, the configuration can be easily extended to multiple delay loops, allowing for a richer recurrent connectivity.
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Efficient  FPGA  Implementations  of  LowMC   and  Picnic

Efficient FPGA Implementations of LowMC and Picnic

Abstract. Post-quantum cryptography has received increased attention in recent years, in particular, due to the standardization effort by NIST. One of the second-round candidates in the NIST post-quantum stan- dardization project is Picnic , a post-quantum secure signature scheme based on efficient zero-knowledge proofs of knowledge. In this work, we present the first FPGA implementation of Picnic . We show how to effi- ciently calculate LowMC , the block cipher used as a one-way function in Picnic , in hardware despite the large number of constants needed dur- ing computation. We then combine our LowMC implementation and efficient instantiations of Keccak to build the full Picnic algorithm. Additionally, we conform to recently proposed hardware interfaces for post-quantum schemes to enable easier comparisons with other designs. We provide evaluations of our Picnic implementation for both, the stan- dalone design and a version wrapped with a PCIe interface, and compare them to the state-of-the-art software implementations of Picnic and sim- ilar hardware designs. Concretely, signing messages on our FPGA takes 0.25 ms for the L1 security level and 1.24 ms for the L5 security level, beating existing optimized software implementations by a factor of 4.
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Adobe LiveCycle Mosaic ES2 Implementations

Adobe LiveCycle Mosaic ES2 Implementations

Mosaic applications are defined in XML and dynamically assembled during runtime on the client. The application XML can be created in any text or XML editor, or even programmatically by another application. The Mosaic 9.0 desktop client includes an early preview version of a Mosaic application design tool that lets you edit and save the application XML in the desktop client. A visual design tool may be available in the future. The first section in the application XML references one or multiple catalogs used by the application. In this section the application developer specifies the URIs and names of the catalogs that store the tiles used in the application. Tiles in an application could be retrieved from multiple catalogs.
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MVC Implementations Playbook. Version 0.92

MVC Implementations Playbook. Version 0.92

ASP.NET MVC is one of the methods of developing ASP.NET applications. ASP.NET MVC Framework is Microsoft’s Web Application development framework, the other one being traditional web forms framework. MVC is a standard design pattern that many developers are familiar with. The Model-View- Controller (MVC) architectural pattern separates an application into three main components: the model, the view, and the controller.

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Large substitution boxes with efficient combinational implementations

Large substitution boxes with efficient combinational implementations

We optimized these 8 distinct circuits for reduced area using a 120nm feature size library with the Synopsys ASIC design tool. To test the effectiveness of our modified Boyar-Peralta minimiza- tion technique, we compared the synthesis results from Synopsys generated using SLP represen- tations of each circuit with this technique to the synthesis results generated from a typical Sum of Products (SOP) representation. More specifically, both representations for each of these circuits were translated to corresponding HDL and then synthesized using a Synopsys to obtain an approxi- mate number of NAND gate equivalents (GEs). We list the results of these two techniques in Table 4.3. We also include results for the three different inversion circuits for GF (2 4 ) defined by the three unique irreducible polynomials p(v) = v 4 +v+1, p(v) = v 4 +v 3 +1, and p(v) = v 4 +v 3 +v 2 +v+1 for elements in a polynomial basis. Note that different area results might be achieved using a dif- ferent CMOS technology. However, we expect the GEs to remain virtually the same in such cases. Also, since the Synopsys tool does not provide the ability to extract the number of logic gates used to implement a particular circuit after the synthesis task, we estimated the GEs by synthesizing and optimizing a single two-input NAND gate using the same cell size library. The result was a combi- national area footprint of 1.0. Thus, to find the gate equivalents for a particular circuit, we simply read the total combinational area footprint.
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Efficient Implementations of NTRU in Wireless Network

Efficient Implementations of NTRU in Wireless Network

O’Rourke first implemented the NTRU core with a gate count of minimum 1483 gates (N = 503) [3]; but it performs star multiplication only. Another design is rea- lized in Kaps’s paper (N = 167) [4]; it performs only en- cryption with an area of 2850 gates and power consump- tion of 15.1 μW at 500 kHz. The most detailed low -cost implementation of NTRU is realized by AC Atici’s [5]. The author presented two compact NTRU architectures (N = 167), one is for encryption only with an area of 2800 gates and a dynamic power consumption of 1.72 μW at 500 kHz. Another is capable of both encryption and decryption, and it consists of 10,500 gates and con- sumes 6 μW dynamic power. Several other papers focus on the optimization of area and power consumption, but only a few works are related to studies on the optimiza- tion of speed.
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Performance Comparison of Software Transactional Memory Implementations

Performance Comparison of Software Transactional Memory Implementations

To ensure comparable performance on both read-dominated and write-dominated workloads Marathe et al. [9] proposed the obstruction-free adaptive software transactional memory (ASTM). This basic ASTM design (referred to simply as “ASTM”) is adaptive in the sense that it can switch between direct or indirect object referencing to take advantage of read- dominated and write-dominated workloads, respectively. There are no levels of indirection to access the object’s data from the object’s metadata with direct object referencing. A history- based heuristic is also deployed to further benefit from workload distribution. Two variants – eager ASTM and lazy ASTM are presented in [9]. In eager ASTM all objects opened in write mode are immediately acquired. The acquiring of writable objects is delayed until commit time in Lazy ASTM. IntSet and LFUCache micro-benchmarks are employed to study the write-dominated workloads. To study read-dominated workloads RBTree and InsetRelease benchmarks are utilized. In all of write-dominated workloads ASTM performance is comparable to DSTM [8]. The basic ASTM and its two variants are clear winners with respect to DSTM in read-dominated workloads.
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Exploiting lattice structures in shape grammar implementations

Exploiting lattice structures in shape grammar implementations

The ability to work with ambiguity and compute new designs based on both defined and emergent shapes are unique advantages of shape grammars. Realizing these benefits in design practice requires the implementation of general purpose shape grammar interpreters that sup- port: (a) the detection of arbitrary subshapes in arbitrary shapes and (b) the application of shape rules that use these subshapes to create new shapes. The complexity of currently avail- able interpreters results from their combination of shape computation (for subshape detection and the application of rules) with computational geometry (for the geometric operations need to generate new shapes). This paper proposes a shape grammar implementation method for three-dimensional circular arcs represented as rational quadratic Bézier curves based on lattice theory that reduces this complexity by separating steps in a shape computation process from the geometrical operations associated with specific grammars and shapes. The method is dem- onstrated through application to two well-known shape grammars: Stiny’s triangles grammar and Jowers and Earl ’ s trefoil grammar. A prototype computer implementation of an inter- preter kernel has been built and its application to both grammars is presented. The use of Bézier curves in three dimensions opens the possibility to extend shape grammar implemen- tations to cover the wider range of applications that are needed before practical implementa- tions for use in real life product design and development processes become feasible.
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Genetic Algorithm: Reviews, Implementations, and Applications

Genetic Algorithm: Reviews, Implementations, and Applications

The genetic programming is the main application of GA. A result of the GA is an amount, whereas the result of genetic programming is a virtual machine process. Es- sentially, this would be the starting of the algorithms that run automatically. But many researchers think how genetic programming and GAs are entirely different things ac- cording to their features. Furthermore, the genetic programming is fundamentally very distinct from another methodology to artificial intelligence, machine learning, neural networks, evolutionary structures, deep learning, or computational reasoning because of how it is genetically motivated; it performs its quest for a result of poverty within the framework of development. Ultimately Genetic Programming helps machines to find solutions without any need for programmers to decide the technique, i.e. what can be performed. That performs such an objective of intelligent coding by genetically modifying a population of automated systems based on the concepts of Natural selec- tion Evolutionary theory or biologically inspired activities. Primarily, sequentially, the genetic design turns a population of software programs into something like a newer generation of software by adding additives to biologically active genetic activities. The Genetic processes involve fusion, mutation, replication, chromosome replication, or genome removal. The Genetic programming is ideally suited to many kinds of chal- lenges. So, there's no transportation option in an automobile. Many approaches operate efficiently at the cost of money, whereas others operate quickly at a high overall possi- bility. Operating a vehicle, thus, entails balancing speeds against protection, and several other factors. Throughout this case, genetic programming would offer a solution that tries to adapt and was the most effective approach from a wide number of factors [41], [42]. To start implementing GA, pursue the following steps:
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