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field programmable gate array implementation

Field Programmable Gate Array Implementation of Active Control Laws for Multi-mode Vibration Damping

Field Programmable Gate Array Implementation of Active Control Laws for Multi-mode Vibration Damping

... This paper investigates the possibility and effectiveness of multi-mode vibration control of a plate through real-time FPGA (Field Programmable Gate Array) implementation. This type of ...

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FIELD PROGRAMMABLE GATE ARRAY IMPLEMENTATION OF EMPIRICAL MODE DECOMPOSITION ALGORITHM FOR ELECTROCARDIOGRAM PROCESSING

FIELD PROGRAMMABLE GATE ARRAY IMPLEMENTATION OF EMPIRICAL MODE DECOMPOSITION ALGORITHM FOR ELECTROCARDIOGRAM PROCESSING

... To implement EMD, each module, that is extrema (local maxima and local minima) extraction, envelope generation, and stopping criterion, was programmed using Matlab then it is converted to Verilog HDL using HDL Coder from ...

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Design of an Asynchronous Processor with Bundled-data Implementation on a Commercial Field Programmable Gate Array

Design of an Asynchronous Processor with Bundled-data Implementation on a Commercial Field Programmable Gate Array

... In this paper, we propose a modeling method and a de- sign flow to design asynchronous processors with bundled- data implementation on FPGAs. We address how to im- plement an asynchronous control circuit on the ...

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Voltage clamp simulation of cardiac excitation: field programmable gate array (fpga) implementation

Voltage clamp simulation of cardiac excitation: field programmable gate array (fpga) implementation

... In this research, voltage clamp simulation is developed based on the LR-I model [8]. The LR-I is developed to model the generation of cardiac excitation for mammalian ventricular cell. This model is chosen because it ...

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U Tube Manometer Calibration using ANFIS

U Tube Manometer Calibration using ANFIS

... This paper deals with the implementation of the Adaptive neuro fuzzy inference system (ANFIS) on a Xilinx based Field Programmable Gate Array Spartan-3E. The implemented hardware is ...

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Implementation of Low Power Memory on FPGA

Implementation of Low Power Memory on FPGA

... and implementation of Random Access Memory (RAM) with reduced power consumption using clock gating technique on a Field Programmable Gate Array ...

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Implementation of Efficient Multilayer Perceptron ANN Neurons on Field Programmable Gate Array Chip

Implementation of Efficient Multilayer Perceptron ANN Neurons on Field Programmable Gate Array Chip

... ANN implementation usually starts with the neuron because it is the basic unit of any neural ...hardware implementation of a neuron has two major ...the implementation of the activation ...hardware ...

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Implementation of Cryptography Algorithms in Field Programmable Gate Array

Implementation of Cryptography Algorithms in Field Programmable Gate Array

... of implementation of selected cryptography algorithms in symmetric and asymmetric category, specifically RSA in symmetric and DES in asymmetric ...The implementation is focused on representation of computer ...

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A Survey on FPGA and ASIC Implementations using RB multiplication to derive

A Survey on FPGA and ASIC Implementations using RB multiplication to derive

... for field programmable gate array (FPGA) and application specific integrated circuit (ASIC) realization of the proposed designs and competing existing designs are ...

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Field Programmable Gate Array–based Implementation of an Improved Algorithm for Objects Distance Measurement (TECHNICAL NOTE)

Field Programmable Gate Array–based Implementation of an Improved Algorithm for Objects Distance Measurement (TECHNICAL NOTE)

... accurate implementation of a distance measuring system which can be used as a part of robot ...FPGA-based implementation of various systems have been done in different ...FPGA-based implementation of ...

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DMA FOR FIELD PROGRAMMABLE GATE ARRAY- BASED RECONFIGURABLE ARCHITECTURES

DMA FOR FIELD PROGRAMMABLE GATE ARRAY- BASED RECONFIGURABLE ARCHITECTURES

... partition, which are often not sufficient for memory-intense applications. However, t h i s imposes many physical design constraints on the FPGA-based implementation, and reduces its potential for flexibility and ...

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Abstract: Field Programmable Gate Array (FPGA) is a general purpose programmable logic device

Abstract: Field Programmable Gate Array (FPGA) is a general purpose programmable logic device

... configurable FFT/IFFT (Fast Fourier Transform / Inverse Fast Fourier Transform) processor [251–254]. FPGAs play a crucial role in networking packet classification, because, due to the scalable and parallel models than ...

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DMA FOR FIELD PROGRAMMABLE GATE ARRAY BASED RECONFIGURABLE ARCHITECTURES

DMA FOR FIELD PROGRAMMABLE GATE ARRAY BASED RECONFIGURABLE ARCHITECTURES

... The original idea was to dynamically reconfigure the FPGA routing resources to implement the crossbar switch, or implementing the crossbar multiplexers using LUTs and reconfiguring their configuration contents by bit ...

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Sparse matrix vector multiplication on a field programmable gate array

Sparse matrix vector multiplication on a field programmable gate array

... Each PE covers a part of the band of the matrix. This means that a PE cannot process every non-zero element. This requires that the non-zero elements have to be divided over the PEs such that they can be processed. This ...

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Booth’s Algorithm Design Using Field Programmable Gate Array

Booth’s Algorithm Design Using Field Programmable Gate Array

... real-time implementation of the hearing aid utilizes a spectral sharpening and noise reduction due to spectral sharpening design for the signal processing, which is illustrated in Figure ...

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Field Programmable Array Implementation of Active Filter Controller.

Field Programmable Array Implementation of Active Filter Controller.

... The controller can be designed using analog chips. However, this method is highly design intensive and lacks flexibility. Alternatively, the controller can be designed in the digital domain, which would involve the use ...

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FPGA Implementation of LTE-Advanced Downlink Physical Layer Transceiver

FPGA Implementation of LTE-Advanced Downlink Physical Layer Transceiver

... and implementation of the LTE-A downlink transmitter and receiver using a Field Programmable Gate Array (FPGA) according to release 10/11 on Virtex 6 XC6VLX240T FPGA kit using Xilinx® ...

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Development and simulation of soft morphological operators for a field programmable gate array

Development and simulation of soft morphological operators for a field programmable gate array

... onto an FPGA by describing the gate level implementation in a layered structure in order to reduce delays and to aid in debugging operations. 12,13 The two main layouts were a multi-k SMO system and a ...

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Implementation of 4-Tap Sequential and Parallel Micro-programmed Based Digital FIR Filter Architecture using VHDL

Implementation of 4-Tap Sequential and Parallel Micro-programmed Based Digital FIR Filter Architecture using VHDL

... using Field Programmable Gate Array ...the implementation of 4-tap sequential and parallel micro- programmed based digital FIR filter using VHDL is presented using 16 bit Wallace tree ...

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An Efficient Implementation of Matrix Multipliers for signal Processing on FPGA

An Efficient Implementation of Matrix Multipliers for signal Processing on FPGA

... and Field Programmable Gate Array (FPGA) implementation of matrix multiplier architectures for use in image and signal processing ...FPGA. Implementation results demonstrate that ...

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