IEEE single precision floating point numbers
Design of High Speed Single Precision Floating Point Multiplier Using Vedic Mathematics
8
Review on 32 bit single precision Floating point unit (FPU) Based on IEEE 754 Standard using VHDL
6
Design of a Single Precision Floating Point Divider and Multiplier with Pipelined Architecture
163
FPGA Implementation of Single Precision Floating Point Multiplier Using High Speed Compressors
7
FPGA Implementation of Low Area Single Precision Floating Point Multiplier
7
Open Source Synthesis and Verification Tool for Fixed to Floating and Floating to Fixed Points Conversions
12
Single Precision Floating Point Arithmetic using VHDL Coding
6
High Speed IEEE 754 Floating Point Multiplier using Different Types of Adder
6
Survey of Matrix Multiplication using IEEE 754 Floating Point for Digital Image Compression
8
Design of a Fused Multiply Add Floating Point and Integer Datapath
168
Comparison of Adders for optimized Exponent Addition circuit in IEEE754 Floating point multiplier using VHDL
6
Design and Simulation of Floating Point FFT Processor Based on Radix-4 Algorithm Using VHDL
7
Virtex 4 Field Programmable Gate Array Based 32 bit FPM
5
FPGA Implementation of Low-Area Floating Point Multiplier Using Vedic Mathematics
5
Performance Evaluation of FPM on Spartan Family FPGAs and Analyze Its Effect on Bonded IOBs
5
TechMemo15rev2_LARC_ComputingUnitInstrs_Dec59.pdf
51
C Building Blocks.pdf
11
FPGA Implementation of Single Precision Floating Point Adder
6
Design of Single Precision Floating Point Multiplication Algorithm with Vector Support
8
Secure Computation on Floating Point Numbers
31