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in-system programmable hardware

Hardware-Software Codesign of a Programmable Wireless Receiver System-on-a-chip

Hardware-Software Codesign of a Programmable Wireless Receiver System-on-a-chip

... As simulation proceeds, it is the job of VHDL code to decide when to trigger disassembled.pl. As shown in fig 5.8 the VHDL procedure trace from file debug.vhd calls another procedure disasC from VHDL package flipkg. This ...

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Naturally Parallel Measuring System Based on FPGA Hardware

Naturally Parallel Measuring System Based on FPGA Hardware

... measuring system to be universal and, depending on the needs, easy to adapt, it was decided to build it based on a programmable FPGA ...the system can be changed any number of ...own hardware ...

13

Design and implementation of a gas 
		identification system on Zynq soc platform

Design and implementation of a gas identification system on Zynq soc platform

... identification system based on PCA and DT ...for hardware acceleration, to design the hardware and to write the required software ...processing system and the programmable logic of the ...

7

Hardware Design of a Flight Control Computer System based on Multi-core Digital Signal Processor and Field Programmable Gate Array

Hardware Design of a Flight Control Computer System based on Multi-core Digital Signal Processor and Field Programmable Gate Array

... control system. The FCS is an embedded system with specialized functions, in which its complexity depends on the required tasks to be performed during the ...

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Reconfigurable Ultrasonic Testing System Development Using Programmable Analog Front End and Reconfigurable  System on Chip Hardware

Reconfigurable Ultrasonic Testing System Development Using Programmable Analog Front End and Reconfigurable System on Chip Hardware

... both hardware and software engineers by using existing ...the system initialization is completed, the profile for the transmitting wave front and gain of the receive channel are configured by programming ...

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Low Complexity Cordic Architecture for MIMO Decoder

Low Complexity Cordic Architecture for MIMO Decoder

... A programmable hardware solution focused on the unique MIMO decoding operations of a MIMO system can help drive down nonrecurring engineering costs, can facilitate system upgrades to take ...

7

GRAPH BASED TEXT REPRESENTATION FOR DOCUMENT CLUSTERING

GRAPH BASED TEXT REPRESENTATION FOR DOCUMENT CLUSTERING

... real-time hardware application is developed around a FPGA hardware architecture that includes embedded processor MicroBlaze on the field programmable gate array ...processor system that can be ...

7

Design and Implementation of Programmable Logic Controller (PLC) Using System on Programmable Chip (SOPC)

Design and Implementation of Programmable Logic Controller (PLC) Using System on Programmable Chip (SOPC)

... ABSTRACT: Programmable logic controller (PLC) is one of the most important components in today’s ...field programmable gate array (FPGA) has been a hot topic because of its parallel execution mechanism and ...

7

Hardware Sharing Design for Programmable Memory Built-In Self Test

Hardware Sharing Design for Programmable Memory Built-In Self Test

... the System-on- Chip ...process. Programmable Built-In Self-Test (P-MBIST) solution provides a certain degree of flexibility with reasonable hardware cost, based on the customized ...a hardware ...

7

GSM remote sensing for transmission line monitoring system using FPGA

GSM remote sensing for transmission line monitoring system using FPGA

... monitoring system to monitor the stealing activities of the copper ...monitoring system for a copper cable transmission line using GSM (Global System for Mobile) ...This system will offer a ...

40

Multiple 3-Phase Motors Control With Password Protection

Multiple 3-Phase Motors Control With Password Protection

... control system, but rather focuses on the supervisory ...of hardware to which it is interfaced, in general via Programmable Logic ...a system that collects data from various sensors at a ...

8

Design and Implementation of Real Time Data Acquisition System in All Programmable System on Chip

Design and Implementation of Real Time Data Acquisition System in All Programmable System on Chip

... as System Level Design (SLD)[18]. The SLD involves both hardware and software design process like modelling, partitioning, integration, synthesis, verification and validation of the complete ...the ...

5

Exploiting the Reconfigurability of Programmable Hardware for Neural Engineering

Exploiting the Reconfigurability of Programmable Hardware for Neural Engineering

... Xilinx System Generator (XSG) ...for hardware implementation. XSG provides a library of hardware blocks that can be converted into hardware description languages for synthesis and bit streams ...

8

Development Of Pesona Risc Microprocessor Architecture In FPGA

Development Of Pesona Risc Microprocessor Architecture In FPGA

... simpler hardware resulting in a high efficient ...communications system including Supervisory Control and Data Acquisition (SCADA), remote monitoring, industrial robotics, home security, appliances, ...

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Parallel Matrix Implementation of an Integer Division Algorithm Using FPGA

Parallel Matrix Implementation of an Integer Division Algorithm Using FPGA

... The modern FPGA devices offer multiple embedded hardware multipliers and even multiply- accumulate cells, well suited for digital signal processing (DSP) applications. However, many control and DSP applications ...

7

Programmable Logic Controllers

Programmable Logic Controllers

... The requirement for higher quality and reliability in control techniques has stemmed from a constant demand for better and more efficient and process machinery. Smart, condensed solid-state electronic devices have made ...

5

MicroLogix 1200 Programmable Controllers

MicroLogix 1200 Programmable Controllers

... module hardware and channel configuration error conditions are reported to the ...Module hardware errors are reported in the controller’s I/O status ...1500 Programmable Controllers Instruction Set ...

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Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block Chaining concept using Verilog and FPGA

Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block Chaining concept using Verilog and FPGA

... In this paper, Data Encryption Standard (DES) and Triple Data Encryption Standard (TDES) algorithm and their efficient hardware implementation in cyclone II Field Programmable Gate Array (FPGA) is analyzed ...

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Resource Efficient Design and Implementation of Standard and Truncated Multipliers using FPGAs

Resource Efficient Design and Implementation of Standard and Truncated Multipliers using FPGAs

... Cryptography requires not only a significant number of multiplication and squaring functions but also large integers [11-12]. Many research efforts have been presented in literature to achieve hardware efficient ...

5

Design and Fabrication of a Programmable Selective Sorting System

Design and Fabrication of a Programmable Selective Sorting System

... sorting system capable of color sensing and spatial orientation of parts to ensure that parts with preselected color and orientation only are allowed to react the delivery point of the ...developed system ...

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