on-chip communication delay
Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip
16
Least Upper Delay Bound for VBR Flows in Networks on Chip with Virtual Channels
41
Weighted Round Robin Configuration for Worst Case Delay Optimization in Network on Chip
16
Inductively Coupled Interconnect for Chip to Chip Communication over Transmission Line
80
LOW POWER AND HIGH PERFORMANCE SERIAL COMMUNICATION INTERFACES FOR ON-CHIP INTERCONNECTS
19
Least Upper Delay Bound for VBR Flows in Networks-on- Chip with Virtual Channels
34
Intra Chip and Inter Chip Wireless Communication Analysis for Millimeter Wave using Miniaturized On Chip Antenna
9
An efficient task mapping algorithm with power-aware optimization for network on chip
17
Dense, Efficient Chip to Chip Communication at the Extremes of Computing
162
Driver Pre-emphasis Signaling for On-Chip Global Interconnects
122
Understanding the Impact of the Interconnection Network Performance of Multi-core Cluster Architectures
8
A Study on Network-On-Chip architecture using Genetic Algorithm
12
DELAY – Disruption Tolerant Network (DTN), its Network Characteristics and Core Applications
7
Causes of Delay in Highway Construction Projects using Relative Importance Index Method
10
Optimized Fault Tolerance in Distributed Environment
6
Dynamical analysis in exponential RED algorithm with communication delay
24
Subwavelength grating enabled on-chip ultra-compact optical true time delay line
10
A Co-Design for CAN-Based Networked Control Systems
10
Delay Resistant Transport Protocol for Deep Space Communication
11
A Petri Net based Method for Analyzing Schedulability of Distributed Real-time Embedded Systems
8