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on-chip communication delay

Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip

Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip

... There are different mathematical formalisms for perfor- mance evaluation in on-chip networks. We have surveyed four popular techniques along with their applications and also reviewed their strengths and weaknesses ...

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Least Upper Delay Bound for VBR Flows in Networks on Chip with Virtual Channels

Least Upper Delay Bound for VBR Flows in Networks on Chip with Virtual Channels

... Network calculus is a mathematical framework for deriving worst-case bounds on maximum latency, backlog, and minimum throughput in network-based systems. It is able to model all traffic patterns with bounds defined by ...

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Weighted Round Robin Configuration for Worst Case Delay Optimization in Network on Chip

Weighted Round Robin Configuration for Worst Case Delay Optimization in Network on Chip

... on Chip (SoC) require different levels of service for different ...the communication result but also the end- to-end delay ...Upper Delay Bound (LUDB) for each packet must not exceed its ...

16

Inductively Coupled Interconnect for Chip to Chip Communication over Transmission Line

Inductively Coupled Interconnect for Chip to Chip Communication over Transmission Line

... frequency is between 9dB and 13dB on each line. This limited gain is enough to correctly detect the signal by the SAFF. The transient response of the input and output signal of the amplifier is shown in figure 4.16. The ...

80

LOW POWER AND HIGH PERFORMANCE SERIAL COMMUNICATION INTERFACES FOR ON-CHIP INTERCONNECTS

LOW POWER AND HIGH PERFORMANCE SERIAL COMMUNICATION INTERFACES FOR ON-CHIP INTERCONNECTS

... the communication energy cost is ...the chip die will be about 22mm on each side with a global wire delay of up to 6–10 clock cycles ...the chip, the cross talk noise, the difficulty of ...

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Least Upper Delay Bound for VBR Flows in Networks-on- Chip with Virtual Channels

Least Upper Delay Bound for VBR Flows in Networks-on- Chip with Virtual Channels

... Network calculus is a mathematical framework for deriving worst-case bounds on maximum latency, backlog, and minimum throughput in network-based systems. It is able to model all traffic patterns with bounds defined by ...

34

Intra Chip and Inter Chip Wireless Communication Analysis for Millimeter Wave using Miniaturized On Chip Antenna

Intra Chip and Inter Chip Wireless Communication Analysis for Millimeter Wave using Miniaturized On Chip Antenna

... on Chip (SoC) is an emerging technology for semiconductor devices that aims for better compaction with reduced interconnects, RC delay, noise, and power ...making communication between the chips ...

9

An efficient task mapping algorithm with power-aware optimization for network on chip

An efficient task mapping algorithm with power-aware optimization for network on chip

... the communication patterns. The communication is distributed on the network according to the requirements from the ...the communication on lines will consume more time. The delay on lines may ...

17

Dense, Efficient Chip to Chip Communication at the Extremes of Computing

Dense, Efficient Chip to Chip Communication at the Extremes of Computing

... The Hogge phase detector has a number of drawbacks that limit its utility in high-speed digital systems. For instance, its output pulse width is proportional to the residual phase error, so good resolution requires ...

162

Driver Pre-emphasis Signaling for On-Chip Global Interconnects

Driver Pre-emphasis Signaling for On-Chip Global Interconnects

... the delay/noise limitation for on-chip global ...the delay goal of cross-chip communication, but even with a suboptimal delay approach, repeaters still consume a significant ...

122

Understanding the Impact of the Interconnection Network Performance of Multi-core Cluster Architectures

Understanding the Impact of the Interconnection Network Performance of Multi-core Cluster Architectures

... evaluate communication performance ...inter-node communication network or focused on high performance multi-core architecture design without considering the effect of interconnection networks on the ...

8

A Study on Network-On-Chip architecture using Genetic Algorithm

A Study on Network-On-Chip architecture using Genetic Algorithm

... the communication traces on the interconnection network. Network-on-chip (NoC) is a new paradigm for designing scalable communication architecture for SoC (system on ...the communication ...

12

DELAY – Disruption Tolerant Network (DTN), its Network Characteristics and Core Applications

DELAY – Disruption Tolerant Network (DTN), its Network Characteristics and Core Applications

... of Delay – Tolerant ...space communication network model using the DTN by transmitting around 200 space images (approx 14 MB) to and from a space craft known as EPOXI – uploaded with DTN software ...

7

Causes of Delay in Highway Construction Projects using Relative Importance Index Method

Causes of Delay in Highway Construction Projects using Relative Importance Index Method

... the delay causing factors in highway construction ...63 delay factors were identified through literature review and discussion with highway construction experts and a questionnaire survey was conducted ...

10

Optimized Fault Tolerance in Distributed Environment

Optimized Fault Tolerance in Distributed Environment

... make the system Fault tolerant and to achieve the reliability of the system many techniques have been developed like transaction, group communication and rollback recovery. One of the Most Common method is applied ...

6

Dynamical analysis in exponential RED algorithm with communication delay

Dynamical analysis in exponential RED algorithm with communication delay

... In this paper, we have investigated the properties of Hopf bifurcation in an exponen- tial RED algorithm with communication delay. It is shown that under certain conditions, the Hopf bifurcation occurs as ...

24

Subwavelength grating enabled on-chip ultra-compact optical true time delay line

Subwavelength grating enabled on-chip ultra-compact optical true time delay line

... time delay realization without using waveguides with different lengths and/or curvy topology, by the precise control of the group index of the waveguides based on ...time delay of each OTTDL’s tap is ...

10

A Co-Design for CAN-Based Networked Control Systems

A Co-Design for CAN-Based Networked Control Systems

... closed-loop communication time delay and we compensate this time delay using the pole-placement design ...the communication time delay compensation and the message scheduling, which ...

10

Delay Resistant Transport Protocol for Deep Space Communication

Delay Resistant Transport Protocol for Deep Space Communication

... space communication. This paper proposes a Delay Resistant Transport Protocol (DR-TCP) for point-to-point communication in deep space exploration ...space communication protocol design and the ...

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A Petri Net based Method for Analyzing Schedulability of Distributed Real-time Embedded Systems

A Petri Net based Method for Analyzing Schedulability of Distributed Real-time Embedded Systems

... reliable communication between tasks is done by bus and bus ...The communication process can follow different protocols, but we don’t focus on modeling communication protocol in this paper, ...

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