Pass transistor logic
A Full swing Ex-OR/Ex-NOR Gate Circuit Using Pass Transistor Logic with Five Transistors
... different logic styles like CPL (Complementary pass transistor logic), DPL (Double pass transistor logic), and PTL (Pass transistor logic) ...the ...
7
LOW POWER MULTIPLEXER BASED FULL ADDER USING PASS TRANSISTOR LOGIC
... Pass transistor logic is used to improve the performance of arithmetic and logic ...This logic can be used to reduce the power dissipation in the system and to increase the speed of ...
6
Design of Parallel in Parallel out Shift Register using Clocked Pass Transistor Logic
... Clocked Pass Transistor Flip-Flop is Designed [5-9] by using Pass Transistor Logic family, In this design only one clocking transistor is used so that it will consume less power ...
5
IMPLEMENTATION OF COMPLEMENTARY PASS TRANSISTOR LOGIC FOR LOW POWER MULTIPLY AND ACCUMULATE CIRCUIT
... low-power logic circuit technique, is used for many VLSI ...restored pass-transistor logic network which is introduced here in this paper is used to perform logic ...
6
LOW-POWER 1-BIT FULL-ADDER CELL USING ENHANCED PASS TRANSISTOR LOGIC AND POWER GATING
... Complementary Pass Transistor Logic (CPL) and sleep transistor provides a drastic reduction in the power compared to CMOS ...sleep transistor is added between actual ground rail and ...
8
Design and Implementation of 4-bit Carry Skip Adder Using NMOS Pass Transistor Logic
... Nmos pass transistor logic which is given in the bellow ...Nmos logic we can design a diagram of full adder using pass transistor logic to reduce area, connectivity, delay ...
5
Low Voltage and Low Power Divide-By- 2-3 Counter Design Using Pass Transistor Logic Circuit Technique
... A state-of-the-art divide-by-2/3 counter design is given in Fig. 1(a) [7]. It contains two E-TSPC-based FFs and two logic gates i.e., an OR gate and an AND gate. When the divide control signal DC is “0”, the OR ...
11
Low Power High Speed Full Adder based on Pass Transistor Logic
... Fig.2 shows the design of the proposed full adder. The XNOR block is used to implement the sum output of the full adder. There are two transistors Mp1 and Mn1 present within the inverter which helps in the generation of ...
5
Ultra Low Power Consumption Military Communication Systems
... gate logic is often used for the design of multiplexers and exclusive OR gates. Since the multiplexers and EXOR gates are the major blocks in many digital systems, the number of transistors and the power consumed ...
6
Design of Double Tail Comparator Using Dual Mode Logic in PTL Design
... mode logic in pass transistor logic design to achieve low power and high performance and shows comparison between optimization of delay between ...in pass transistor design have ...
7
High Speed Tree based 64 Bit Binary Comparator using New Approach
... (pass transistor logic) is to use purely NMOS Pass Transistors network for logic operation ...of pass-transistor logic style compared to the CMOS logic style ...
5
Low Power 32-bit Improved Carry Select Adder based on MTCMOS Technique
... ABSTRACT: The raise in requirement for mobile and electronic devices is causing the necessity of low power. This paper presents the design of Carry Select Adder using MTCMOS technique. A 32-bit CSA is designed. The ...
7
ADIABATIC LOGIC FOR LOW POWER DIGITAL DESIGN
... Adiabatic logic which is proved to be the excellent technique to design the low power digital ...adiabatic logic with complementary energy path dual pass transistor logic ...
9
Reduction of Leakage Power using Stacking Power Gating Technique in Different CMOS Design Style at 45Nanometer Regime
... As transistor sizes scale down and levels of integration increase, leakage power has become a vital downside in modern low-power VLSI ...between logic stacks and power supply ...from transistor ...
8
Design of Parallel Self Timed Adder
... Complementary pass transistor logic (CPL), Double pass transistor logic (DPL), Transmission gate (TGA), Transmission function (TFA), New 14T, Hybrid CMOS, HPSC, Pseudo nMOS, GDI ...
7
Power and Area Efficient Error Tolerant Adder Using Pass Transistor XOR Logic in VLSI Circuits
... electronics, pass transistor logic (PTL) describes several logic families used in the design of integrated ...different logic gates, by eliminating redundant transistors. ...
5
An Approach to Design a New Multifunctional Reversible Logic Gate (MRLG)
... The Pass transistor logic (PT) realization of MRLG gate is shown in fig.3. Consider the input are A= ‘1’, B= ‘1’, C= ‘0’ and D= ‘1’. Since A= ‘1’ the transistor Q1 is OFF and Q2 is ON. So the ...
8
1. Design of low power and high speed multiplier
... applying Pass Transistor Logic (PTL) in Conventional Full Adder to improve the efficiency of the conventional multiplier ...using pass transistor ...
7
Implementation of Modified Baugh Wooley Signed Multiplier
... ABSTRACT: Adders and multipliers are fundamental building blocks in many computational units. The project is implemented on Wallace signed multiplier circuit in ASIC through modified Baugh-Wooley approach using standard ...
5
Design the 2X1 MUX with 2T Logic and Comparing the Power Dissipation and Area with Different Logics
... combinational logic circuit designed to switch one of several input lines through to a single common output line by the application of a control ...and pass-transistor logic ...on ...
7