Phase Locked Loop

This paper presents a glitch free NAND based digitally controlled delay lines for the avoidance of glitches by using different driving circuits. In glitch free NAND based DCDL, driving circuits are used to generate the control bits which consumes considerable amount of power and delay time. Driving techniques suggested here are dual edge triggered sense amplifier based flip-flop and NIKOLIC sense amplifier based flip-flop, which comparatively have reduced power consumption and delay time. The proposed NAND based DCDL have been designed in 90nm CMOS technology and various performances of these techniques are compared by the simulation parameters like power, area and delay. In addition, the proposed DCDL is adopted in phase locked loop.

Phase locked loop (PLL) is nowadays have become one of the most important parameters of the modern electronics and communication circuits and of their designs. Work on PLL has started in the late thirties of the 19th century as a part of rapid growth in the IC technologies. Going by the history of the phase locked loop, the early PLL based IC was introduced in some mid-range of 1960-1965. Which was mainly designed using with the help of analog component .now a day since more focus on work is over the integrated circuit, hence the requirement is on the construction of phase locked loop to achieve better results with a better reliable status. Nowadays entire PLL is in general integrated into a single chipset giving a major economic boost. Still, this area is widely considered for research and development because of its low power, high radio frequency aspect and it's also very widely used in low power, high-frequency range MOSFET application. Earlier research was mostly based on the outlines and working of phase locked loop, now research in this field is mostly dedicated towards its application and how we can fit it in modern electronics designs. The widest application of the phase locked loop is in frequency synthesis and in generating high radio frequency. Since a crystal oscillator cannot generate high frequency and hence here, PLL comes into the picture. A phase-locked loop since it comes under the RF

A modern advance technology in integrated circuit technology makes fabrication processes very suitable for digital designs. Small-area and low-voltage designs are mandated by market requirements. Another advantage of digital PLL is easy to redesign with the process changes. Since analog blocks are present in a number of digital and mixed-signal ICs, their redesign is an important factor in the release of a new product. However, the performance requirements of analog blocks necessitates a complete redesign in a new process, thereby increasing the design cycle time. Reducing the amount of analog circuitry can improve the redesign of these mixed-signal ICs. A Phase Locked Loop is mainly used for the purpose of synchronization of the frequency and phase of a locally generated signal with that of an incoming signal. There are three components in a PLL. The Phase Frequency detector (PFD), the loop filter and the Voltage Controlled Oscillator (VCO). The VCO is the heart of any PLL. The mechanism by which this VCO operates decides the type of the PLL circuit being used. There are basically four types of constructing PLLs namely Linear PLL (LPLL), Digital PLL (DPLL) and All Digital PLL (ADPLL).

Abstract—Due to the important relationship between ultrasonic velocity and some properties of sample, the measurement of velocity of ultrasound is widely needed in various fields. In this paper, based on phase-locked loop technique, a new hybrid circuit is designed for ultrasonic velocity measurement and named as UV-PLL. In order to improve the stability of phase and achieve the ability of fast locking, an auxiliary capturing circuit, which consists of phase shift circuit and capturing circuit, is designed and implemented in this module. Additionally, two methods for estimating the propagation delay is compared and described in detail. The UV-PLL module is validated through the ultrasonic velocity measurement in distilled water at different temperatures. Experimental results show that the maximum relative deviation of velocity measurement is less than 0.15% and the loop can be quickly locked, indicating that this module can meet the requirements of online measurement and can be widely applied.

Phase-Locked Loop (PLL) is one of the most important synchronizing circuits used in transceivers, communication systems, etc. Conventional digital PLL (DPLL) should be modified to achieve fast locking. Different techniques have been used to obtain fast locking DPLLs [1-7]. In this paper, a novel DPLL is proposed to achieve fast locking by varying the PLL bandwidth. Wide bandwidth is used when the PLL is in the out-of-lock state, while the narrow bandwidth is used when the PLL is in the lock state. This can be accomplished by applying additional current to the conventional charge pump current in the out- of- lock state.

There are various known frequency synthesizer architectures of which the most important ones are outlined in [3, Chapter 1.3]. That thesis builds the case for the Phase-Locked Loop (PLL) as being the best choice for a high-speed low jitter frequency synthesizer. Looking at PLL publications, more often than not the jitter and power consumption are the key performance metrics and therefore focus of the publication. In order to objectively compare PLL implementations with respect to jitter and power consumption, a Figure-Of-Merit (FOM) was derived in [4]. This FOM indicates how far from ideal a PLL is with respect to jitter versus power dissipation. A lower FOM indicates a better design.

means for adjusting the increment control input of the charge pump so that it monotonically decreases from an initial relatively high value at a fll"St time when the phase locked loop be[r]

multiple application in multiple areas like wireless communication and instrumentation engineering. In the microwave frequency range these all are applied in frequency synthesis and phase extraction among others. Phase-locked loop can be used to achieve an exact phase and frequency relation between two independent sources. Phased lock loop is a control system that makes an output signal whose frequency is depends on the input phase difference. Phase detector compares phase of input signal with the phase derived from its output oscillator adjusts the frequency of its oscillator to maintain the phase matches. The signal from the phase detector is used to control the oscillator in a feedback loop. As such an operational device the PLL has wide range of applications in telecommunication, computers sciences and electronic system applications. The phase locked loop consists of voltage controlled oscillator and a phase detector. Monolithic phase locked loops have been used for clock recovery and data in communication system, in microprocessor for clock generation and frequency synthesis in wireless application.

Abstract -We model and simulate an analog phase-locked loop for frequency hopping spread spectrum based applications such as Bluetooth. The modeling and simulation method uses an analog phase-locked loop, consisting of multiplier, loop filter, voltage controlled oscillator and generates hopping carriers up to 2.502 GHz. The generated carrier frequency holds at a particular hop for a maximum dwell time of 50µS. The complete simulation program for the system is written in Turbo C. The MATLAB program is used for graphical analysis of simulated data. The simulation results show that the generated carriers settle around 60 µS for maximum hopping carrier frequency of 100 MHz. The measured carrier frequencies and settling times are found comparable with standard values and related works.

the phase of the input signals, automatically raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase. It is an example of a control system using negative feedback which tracks the phase changes that are within the bandwidth of the PLL. A PLL also multiplies a low- frequency reference clock to produce a high-frequency clock. The phase-locking is done after many iterations of comparing the reference and feedback signals. As the phase is locked then the output of PLL will be constant. Phase- locked loop consist of phase/frequency detector, charge pump, low pass filter, voltage controlled oscillator and programmable divider. The phase-frequency detector detects any phase differences between the input reference signal and the feedback signal generate digital error pulse that digital error pulse converted in to analog error current by charge pump that provided to low pass filter which integrates error current to generate control voltage supplied to VCO which converts that control voltage in to signal with appropriate frequency. As the control voltage is increase than VCO signal frequency also increase. The output signal from VCO is divided by a programmable divider and compared with input signal in phase frequency detector and generate error pulse. This process is continue until the phase difference between the input reference signal and the feedback VCO signal is zero or constant that is the locked state. This process is called phase tracking. The time PLL takes to respond to change in the input frequency is called as lock time and the range of frequency over which the PLL can stay in lock is called the hold in range. Ideally, the lock time should be small as possible. It plays an important role in wide range of applications including clock de-skew for high-speed digital and mixed-signal IC’s, clocks synthesis, carrier recovery, clock recovery, modulation and demodulation of frequency or phase and filter tuning [8].

ABSTRACT: A balanced optical phase-locked loop (OPLL) has been investigated through simulation experiment, considering the photo-detector shot noise, laser phase noise and loop propagation delay into account. This optical balanced loop contains an additional electro-optic phase modulator in the phase-locking branch to improve the tracking capability of the loop. The tracking behaviour of the OPLL are investigated in terms of pull-in behaviour and phase- error variance in presence of loop-delay. The modified loop achieves lock-in state in a relatively smaller acquisition time than the conventional OPLL. In this OPLL, the line-width requirement can be easily increased to a large value, by changing the phase control parameter.

ABSTRACT:This paper describes a design of phase locked loop system with low power and minimum jitter. PLLs with high speed, low noise and wide bandwidth with fast acquistion time are preferred. A PFD with low dead zone, charge pump with passive low pass filter and a low noise, wide tuning VCO are integrated in the PLL system. A Telescopic OTA based VCO with wide tuning range of 450MHz to 1.9GHz and power consumption of 0.30mW is designed.. The PFD modeled is using 15 transistor and conventional charge pump with second order loop filter is used. Integrating this VCO in a PLL system offers low jitter and wide bandwidth. The results prove that maximum pull-in time is 150ns and the power consumed by this PLL system is 606uW at 1.5GHz.Measured jitter is 30ps in this PLL. KEYWORDS: Phase Locked Loop (PLL), Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter, Voltage Controlled Oscillator (VCO), Lock-in range, Lock time, Jitter

Chaos in closed phase locked loops has been researched by many researchers in various institutions around the world for at past few years. Closed phase locked loops similar to many chaotic systems that are close to Chua’s circuit series [8], Josephson junctions [9] and Van der Pol oscillator [10] have been considered extensively in this work. A more recent study was made on chaos in closed phase locked loop has stretched beyond analysis of chaotic behavior. The general no- tion of chaos synchronization was used to build a communication system that will ensure the security of information transmitted with it.

The phase-locked loop (PLL) is the most critical procedure for era of multiplexing of message signals. It permits the era of variable output frequency with a similar dependability of a precious stone oscillator by methods for feedback. In this work mathematical description of the multiplier operation is presented, and characteristic of the PD for various signal waveforms is presented. The characteristics of a PD obtained in this work are in line with the well-known characteristics for the sinusoidal and square waveforms. PLL models in the phase-frequency domain are justified using the averaging method by Krylov-Bogolyubov. Numerical simulation confirms the adequacy of the derived models.

ABSTRACT: This work implements an energy efficient and high speed phase locked loop (PLL) . The main block of PLL is Phase Frequency Detector (PFD), Charge Pump (CP), Low pass filter and a Voltage controlled Oscillator (VCO). The Phase frequency detector used here has been implemented with True Single Phase Clocked logic (TSPC) D flip-flop. This PFD is used to increase the locking performance and to reduce the dead zone. Charge pump is used for the DC-DC conversion. The proposed charge pump avoids charge injection, clock feed through effects and this reduces the ripples in the output. Ring oscillator is used as Voltage Control Oscillator which requires less layout area and has a wide frequency tuning range. Supply voltage of 3V is used and the power dissipated is 11.409 mW. TSMC 0.35- µm technology is used to implement the proposed phase locked loop.

In a phase-locked loop, the error signal from the phase comparator is the contrast between the information frequency or phase and that of the signal input. The framework will compel the frequency or phase error signal to zero in the relentless state. The regular conditions for a negative-feedback framework apply.

The analog PLL or the Linear PLL has been in use since a long time. It basically uses a multiplier circuit for serving the purpose of the PFD and a first order filter for the loop filter and a typical analog VCO. Though the name Digital is present in the DPLL, it’s not exactly a complete Digital PLL. The All Digital PLL makes an attempt at digitizing all the three components required for the operation of a phase locked loop.

The purpose of this project is to familiarise in designing and constructing a 30 MHz Phase-Locked Loop Coherent Receiver by computer simulation, taking account the requirements for each [r]

This paper deals with performance analysis and implementation of a three phase inverter fed induction motor (IM) drive system. The closed loop control scheme of the drive utilizes the Digital Phase Locked Loop (DPLL). The DPLL is safely implemented all around the well known integrated circuit DPLL 4046. An ex- perimental verification is carried out on one kw scalar controlled IM system drives for a wide range of speeds and loads appliance. This presents a simple and high performance solution for industrial applications.

The energy operator phase locked loop (EO-PLL) has been introduced and s detailed review and a coherent comparison for grid voltages synchronisation has been performed on four different schemes. All these schemes have been tested and the comparison has been verified through simulation results. The common trait in all these schemes apart from the EO-PLL is that they all aim to extract the fundamental PSCs from the measured grid voltages signals and the phases are either estimated directly from the extracted PSCs or conventional SRF-PLL scheme. Every scheme has its own merits and its application should depend on the severity of the distortions and the resources available (i.e. hardware or software) for the implementation. Based on its simplicity and faster transient response the EO-PLL offers a relatively definitive solution for synchronisation of grid voltages.